# RUN: llvm-mc -triple=xtensa -mattr=+rvector -disassemble %s | FileCheck -check-prefixes=CHECK-RVECTOR %s
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s

## Verify that binary code is correctly disassembled with
## rvector option enabled. Also verify that dissasembling without
## rvector option generates warnings.

[0x30,0xe7,0x61]
# CHECK-RVECTOR: xsr a3, vecbase
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding