# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
# RUN: llvm-mc -triple=xtensa -mattr=+dfpaccel -disassemble %s | FileCheck -check-prefixes=CHECK-DFPACCEL %s
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s

## Verify that binary code is correctly disassembled with
## DFPACCEL option enabled. Also verify that dissasembling without
## DFPACCEL option generates warnings.

[0xa0,0x3e,0xe3]
# CHECK-DFPACCEL: rur	a3, f64r_lo
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding

[0xb0,0x3e,0xe3]
# CHECK-DFPACCEL: rur	a3, f64r_hi
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding

[0xc0,0x3e,0xe3]
# CHECK-DFPACCEL: rur	a3, f64s
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding