# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefix=GCN %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefixes=GFX11,W32 %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefixes=GFX11,W64 %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefix=GFX12 %s

# GCN: [[@LINE+1]]:1: warning: invalid instruction encoding
0xdf,0x00,0x00,0x02

# this is s_singleuse_vdst 0x1234, which is only valid on gfx1150
# GFX11: [[@LINE+1]]:1: warning: invalid instruction encoding
0x34,0x12,0x93,0xbf

# this is s_waitcnt_vscnt exec_hi, 0x1234, which is valid on gfx11, but not on gfx12
# GFX12: [[@LINE+1]]:1: warning: invalid instruction encoding
0x34,0x12,0x7f,0xbc

# W32: v_dual_add_f32 v5, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, v3, v1, 0xaf123456 ; encoding: [0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf]
# W64: [[@LINE+1]]:1: warning: invalid instruction encoding
0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf

# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c

# W32: v_wmma_f32_16x16x16_f16 v[16:23], 1.0/*Invalid immediate*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
# W64: v_wmma_f32_16x16x16_f16 v[16:19], 1.0/*Invalid immediate*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
0x10,0x40,0x40,0xcc,0xf2,0x10,0x42,0x1c # src0 1.0

# W32: v_wmma_f32_16x16x16_f16 v[16:23], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
# W64: v_wmma_f32_16x16x16_f16 v[16:19], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c # src0 sgpr0

# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b # src2 1.0

# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], s[0:3]/*Invalid register, operand has 'VReg_128' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18 # src2 sgpr0

# this is ds_add_f32 with gds bit which is not valid on gfx12+
# GFX12: [[@LINE+1]]:1: warning: invalid instruction encoding
0x00,0x00,0x56,0xd8,0x00,0x01,0x00,0x00

# this is image_msaa_load where samp field for gfx12 VSAMPLE is not all zeros
# GFX12: [[@LINE+1]]:1: warning: invalid instruction encoding
0x06,0x00,0x46,0xe4,0x01,0x10,0x80,0x00,0x05,0x06,0x07,0x00

# This is ds_read_b32 with gds bit which is not valid on gfx90a.
# GFX90A: [[@LINE+1]]:1: warning: invalid instruction encoding
0x00,0x00,0x6d,0xd8,0x01,0x00,0x00,0x00