Index of /~tb-builder/tor-browser-build/git_clones/llvm-project/llvm/test/CodeGen/RISCV

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[ ]atomic-rmw.ll2024-07-18 02:23 766K 
[ ]half-convert.ll2024-07-18 02:23 303K 
[ ]nontemporal.ll2024-07-18 02:23 226K 
[ ]atomic-cmpxchg.ll2024-07-18 02:23 185K 
[ ]forced-atomics.ll2024-07-18 02:23 180K 
[ ]atomic-signext.ll2024-07-18 02:23 178K 
[ ]xaluo.ll2024-07-18 02:23 177K 
[ ]half-round-conv.ll2024-07-18 02:23 169K 
[ ]half-round-conv-sat.ll2024-07-18 02:23 160K 
[ ]vararg.ll2024-07-18 02:23 134K 
[ ]callee-saved-gprs.ll2024-07-18 02:23 132K 
[ ]push-pop-popret.ll2024-07-18 02:23 126K 
[ ]branch-relaxation.ll2024-07-18 02:23 120K 
[ ]interrupt-attr.ll2024-07-18 02:23 119K 
[ ]fpclamptosat.ll2024-07-18 02:23 116K 
[ ]condops.ll2024-07-18 02:23 115K 
[ ]wide-scalar-shift-legalization.ll2024-07-18 02:23 111K 
[ ]imm.ll2024-07-18 02:23 111K 
[ ]calling-conv-ilp32e.ll2024-07-18 02:23 111K 
[ ]half-arith.ll2024-07-18 02:23 107K 
[ ]ctlz-cttz-ctpop.ll2024-07-18 02:23 102K 
[ ]pr69586.ll2024-07-18 02:23 99K 
[ ]half-intrinsics.ll2024-07-18 02:23 98K 
[ ]double-convert.ll2024-07-18 02:23 92K 
[ ]wide-scalar-shift-by-byte-multiple-legalization.ll2024-07-18 02:23 87K 
[ ]bittest.ll2024-07-18 02:23 84K 
[ ]rotl-rotr.ll2024-07-18 02:23 78K 
[ ]callee-saved-fpr32s.ll2024-07-18 02:23 76K 
[ ]half-convert-strict.ll2024-07-18 02:23 75K 
[ ]llvm.frexp.ll2024-07-18 02:23 74K 
[ ]inline-asm-mem-constraint.ll2024-07-18 02:23 74K 
[ ]float-convert.ll2024-07-18 02:23 72K 
[ ]half-br-fcmp.ll2024-07-18 02:23 63K 
[ ]float-intrinsics.ll2024-07-18 02:23 62K 
[ ]double-arith.ll2024-07-18 02:23 62K 
[ ]double-fcmp-strict.ll2024-07-18 02:23 61K 
[ ]double-round-conv-sat.ll2024-07-18 02:23 61K 
[ ]bfloat-convert.ll2024-07-18 02:23 58K 
[ ]double-intrinsics-strict.ll2024-07-18 02:23 58K 
[ ]spill-fill-fold.ll2024-07-18 02:23 55K 
[ ]atomic-load-store.ll2024-07-18 02:23 54K 
[ ]float-round-conv-sat.ll2024-07-18 02:23 54K 
[ ]double-intrinsics.ll2024-07-18 02:23 53K 
[ ]float-intrinsics-strict.ll2024-07-18 02:23 51K 
[ ]fastcc-without-f-reg.ll2024-07-18 02:23 51K 
[ ]float-round-conv.ll2024-07-18 02:23 51K 
[ ]double-round-conv.ll2024-07-18 02:23 50K 
[ ]atomicrmw-uinc-udec-wrap.ll2024-07-18 02:23 50K 
[ ]sextw-removal.ll2024-07-18 02:23 49K 
[ ]rv64i-exhaustive-w-insts.ll2024-07-18 02:23 49K 
[ ]prefetch.ll2024-07-18 02:23 48K 
[ ]short-forward-branch-opt.ll2024-07-18 02:23 48K 
[ ]bswap-bitreverse.ll2024-07-18 02:23 47K 
[ ]make-compressible.mir2024-07-18 02:23 47K 
[ ]callee-saved-fpr64s.ll2024-07-18 02:23 47K 
[ ]inline-asm-d-abi-names.ll2023-07-06 06:03 46K 
[ ]inline-asm-f-abi-names.ll2023-07-06 06:03 45K 
[ ]rv64zba.ll2024-07-18 02:23 45K 
[ ]stack-realignment.ll2024-07-18 02:23 45K 
[ ]inline-asm-abi-names.ll2024-07-18 02:23 44K 
[ ]rv64zbb.ll2024-07-18 02:23 44K 
[ ]mul.ll2024-07-18 02:23 44K 
[ ]srem-vector-lkk.ll2024-07-18 02:23 43K 
[ ]select.ll2024-07-18 02:23 43K 
[ ]rv32zbb.ll2024-07-18 02:23 42K 
[ ]float-fcmp-strict.ll2024-07-18 02:23 41K 
[ ]memset-inline.ll2024-07-18 02:23 39K 
[ ]calling-conv-ilp32-ilp32f-ilp32d-common.ll2024-07-18 02:23 38K 
[ ]double-br-fcmp.ll2024-07-18 02:23 37K 
[ ]float-arith.ll2024-07-18 02:23 37K 
[ ]rv64m-exhaustive-w-insts.ll2024-07-18 02:23 37K 
[ ]double-arith-strict.ll2024-07-18 02:23 36K 
[ ]interrupt-attr-nocall.ll2024-07-18 02:23 35K 
[ ]div.ll2024-07-18 02:23 35K 
[ ]half-fcmp-strict.ll2024-07-18 02:23 35K 
[ ]overflow-intrinsics.ll2024-07-18 02:23 35K 
[ ]machine-combiner.ll2024-07-18 02:23 35K 
[ ]urem-vector-lkk.ll2024-07-18 02:23 34K 
[ ]xtheadmemidx.ll2024-07-18 02:23 34K 
[ ]double-convert-strict.ll2024-07-18 02:23 33K 
[ ]fold-addi-loadstore.ll2024-07-18 02:23 33K 
[ ]float-br-fcmp.ll2024-07-18 02:23 33K 
[ ]llvm.exp10.ll2024-07-18 02:23 33K 
[ ]attributes.ll2024-07-18 02:23 32K 
[ ]setcc-logic.ll2024-07-18 02:23 32K 
[ ]zfhmin-half-intrinsics-strict.ll2024-07-18 02:23 31K 
[ ]memcpy-inline.ll2024-07-18 02:23 30K 
[ ]ctz_zero_return_test.ll2024-07-18 02:23 30K 
[ ]unfold-masked-merge-scalar-variablemask.ll2024-07-18 02:23 30K 
[ ]double-fcmp.ll2024-07-18 02:23 29K 
[ ]half-fcmp.ll2024-07-18 02:23 29K 
[ ]double-select-fcmp.ll2024-07-18 02:23 29K 
[ ]half-select-fcmp.ll2024-07-18 02:23 28K 
[ ]signed-truncation-check.ll2024-07-18 02:23 28K 
[ ]lack-of-signed-truncation-check.ll2024-07-18 02:23 28K 
[ ]rv64zbs.ll2024-07-18 02:23 28K 
[ ]condbinops.ll2024-07-18 02:23 27K 
[ ]div-by-constant.ll2024-07-18 02:23 27K 
[ ]zfh-half-intrinsics-strict.ll2024-07-18 02:23 27K 
[ ]srem-seteq-illegal-types.ll2024-07-18 02:23 26K 
[ ]vp-splice-mask-vectors.ll2024-07-18 02:23 26K 
[ ]float-convert-strict.ll2024-07-18 02:23 25K 
[ ]addimm-mulimm.ll2024-07-18 02:23 25K 
[ ]rv64xtheadbb.ll2024-07-18 02:23 25K 
[ ]bfloat.ll2024-07-18 02:23 23K 
[ ]stack-folding.ll2024-07-18 02:23 23K 
[ ]float-arith-strict.ll2024-07-18 02:23 23K 
[ ]calling-conv-half.ll2024-07-18 02:23 23K 
[ ]jumptable.ll2024-07-18 02:23 23K 
[ ]copysign-casts.ll2024-07-18 02:23 22K 
[ ]nontemporal-scalable.ll2024-07-18 02:23 22K 
[ ]rv32zbs.ll2024-07-18 02:23 21K 
[ ]libcall-tail-calls.ll2024-07-18 02:23 21K 
[ ]urem-seteq-illegal-types.ll2024-07-18 02:23 20K 
[ ]bfloat-br-fcmp.ll2024-07-18 02:23 20K 
[ ]shifts.ll2024-07-18 02:23 20K 
[ ]select-binop-identity.ll2024-07-18 02:23 20K 
[ ]rem.ll2024-07-18 02:23 20K 
[ ]machine-cse.ll2024-07-18 02:23 20K 
[ ]i64-icmp.ll2023-07-21 02:22 19K 
[ ]half-arith-strict.ll2024-07-18 02:23 19K 
[ ]float-fcmp.ll2024-07-18 02:23 18K 
[ ]half-mem.ll2024-07-18 02:23 18K 
[ ]float-bit-preserving-dagcombines.ll2024-07-18 02:23 18K 
[ ]min-max.ll2024-07-18 02:23 18K 
[ ]vp-splice.ll2024-07-18 02:23 17K 
[ ]iabs.ll2024-07-18 02:23 17K 
[ ]sext-zext-trunc.ll2024-07-18 02:23 17K 
[ ]half-select-icmp.ll2024-07-18 02:23 17K 
[ ]split-udiv-by-constant.ll2024-07-18 02:23 17K 
[ ]i32-icmp.ll2023-07-21 02:22 17K 
[ ]stack-inst-compress.mir2024-07-18 02:23 16K 
[ ]calling-conv-lp64-lp64f-lp64d-common.ll2024-07-18 02:23 16K 
[ ]bfloat-arith.ll2024-07-18 02:23 16K 
[ ]double-select-icmp.ll2024-07-18 02:23 15K 
[ ]rv64zbb-zbkb.ll2023-07-21 02:22 15K 
[ ]atomic-cmpxchg-branch-on-result.ll2024-07-18 02:23 15K 
[ ]atomic-rmw-discard.ll2024-07-18 02:23 14K 
[ ]rv32xtheadbb.ll2024-07-18 02:23 14K 
[ ]memcpy.ll2024-07-18 02:23 14K 
[ ]rv32zba.ll2024-07-18 02:23 14K 
[ ]double-mem.ll2024-07-18 02:23 14K 
[ ]double-maximum-minimum.ll2024-07-18 02:23 14K 
[ ]alu64.ll2024-07-18 02:23 13K 
[ ]vp-splice-mask-fixed-vectors.ll2024-07-18 02:23 13K 
[ ]cmov-branch-opt.ll2024-07-18 02:23 13K 
[ ]vp-splice-fixed-vectors.ll2024-07-18 02:23 13K 
[ ]float-select-fcmp.ll2024-07-18 02:23 13K 
[ ]srem-lkk.ll2024-07-18 02:23 13K 
[ ]machineoutliner-pcrel-lo.mir2024-07-18 02:23 12K 
[ ]hoist-global-addr-base.ll2024-07-18 02:23 12K 
[ ]stack-slot-coloring.mir2024-07-18 02:23 12K 
[ ]div-pow2.ll2023-07-21 02:22 12K 
[ ]stack-store-check.ll2024-07-18 02:23 12K 
[ ]unaligned-load-store.ll2024-07-18 02:23 12K 
[ ]make-compressible-rv64.mir2023-07-21 02:22 12K 
[ ]rv64-stackmap.ll2024-07-18 02:23 12K 
[ ]rv32zbb-zbkb.ll2024-07-18 02:23 12K 
[ ]select-const.ll2024-07-18 02:23 12K 
[ ]calling-conv-ilp32-ilp32f-common.ll2024-07-18 02:23 11K 
[ ]select-optimize-multiple.ll2024-07-18 02:23 11K 
[ ]xtheadmempair.ll2024-07-18 02:23 11K 
[ ]split-urem-by-constant.ll2024-07-18 02:23 11K 
[ ]calling-conv-ilp32d.ll2024-07-18 02:23 11K 
[ ]float-maximum-minimum.ll2024-07-18 02:23 11K 
[ ]shlimm-addimm.ll2024-07-18 02:23 10K 
[ ]tls-models.ll2024-07-18 02:23 10K 
[ ]calling-conv-sext-zext.ll2024-07-18 02:23 10K 
[ ]calls.ll2024-07-18 02:23 10K 
[ ]sadd_sat_plus.ll2024-07-18 02:23 10K 
[ ]double_reduct.ll2024-07-18 02:23 10K 
[ ]mem64.ll2024-07-18 02:23 10K 
[ ]double-calling-conv.ll2024-07-18 02:23 10K 
[ ]saverestore.ll2024-07-18 02:23 9.9K 
[ ]select-cc.ll2024-07-18 02:23 9.8K 
[ ]O3-pipeline.ll2024-07-18 02:23 9.8K 
[ ]elf-preemption.ll2023-07-21 02:22 9.7K 
[ ]compress-opt-branch.ll2024-07-18 02:23 9.6K 
[ ]rv64zfhmin-half-convert.ll2024-07-18 02:23 9.6K 
[ ]fmax-fmin.ll2024-07-18 02:23 9.6K 
[ ]mem.ll2024-07-18 02:23 9.6K 
[ ]bfloat-select-fcmp.ll2024-07-18 02:23 9.6K 
[ ]ssub_sat_plus.ll2024-07-18 02:23 9.4K 
[ ]half-bitmanip-dagcombines.ll2024-07-18 02:23 9.3K 
[ ]calling-conv-lp64e.ll2024-07-18 02:23 9.2K 
[ ]signbit-test.ll2023-07-21 02:22 9.2K 
[ ]pr58286.ll2023-07-21 02:22 8.9K 
[ ]sdiv-pow2-cmov.ll2024-07-18 02:23 8.9K 
[ ]regalloc-last-chance-recoloring-failure.ll2024-07-18 02:23 8.8K 
[ ]zbb-cmp-combine.ll2024-07-18 02:23 8.6K 
[ ]rv64zbkb.ll2024-07-18 02:23 8.6K 
[ ]float-mem.ll2024-07-18 02:23 8.5K 
[ ]double-zfa.ll2024-07-18 02:23 8.5K 
[ ]rv32xtheadba.ll2024-07-18 02:23 8.4K 
[ ]alu16.ll2023-07-21 02:22 8.4K 
[ ]rv64xtheadba.ll2024-07-18 02:23 8.3K 
[ ]frame-info.ll2024-07-18 02:23 8.2K 
[ ]sadd_sat.ll2024-07-18 02:23 8.1K 
[ ]rv64zfhmin-half-convert-strict.ll2024-07-18 02:23 8.0K 
[ ]alu8.ll2023-07-21 02:22 8.0K 
[ ]alu32.ll2023-07-06 06:03 7.9K 
[ ]urem-lkk.ll2024-07-18 02:23 7.9K 
[ ]calling-conv-ilp32f-ilp32d-common.ll2024-07-18 02:23 7.7K 
[ ]tail-calls.ll2024-07-18 02:23 7.7K 
[ ]calling-conv-lp64.ll2024-07-18 02:23 7.6K 
[ ]remat.ll2024-07-18 02:23 7.6K 
[ ]float-select-icmp.ll2024-07-18 02:23 7.6K 
[ ]ssub_sat.ll2024-07-18 02:23 7.5K 
[ ]compress-opt-select.ll2024-07-18 02:23 7.5K 
[ ]select-optimize-multiple.mir2023-07-21 02:22 7.4K 
[ ]calling-conv-ilp32.ll2024-07-18 02:23 7.4K 
[ ]reserved-regs.ll2024-07-18 02:23 7.4K 
[ ]selectcc-to-shiftand.ll2024-07-18 02:23 7.4K 
[ ]shift-amount-mod.ll2024-07-18 02:23 7.2K 
[ ]uadd_sat_plus.ll2024-07-18 02:23 7.2K 
[ ]zcmp-prolog-epilog-crash.mir2024-07-18 02:23 7.0K 
[ ]bitreverse-shift.ll2023-07-21 02:22 7.0K 
[ ]rv64zfh-half-convert.ll2024-07-18 02:23 7.0K 
[ ]neg-abs.ll2024-07-18 02:23 7.0K 
[ ]rv64f-float-convert.ll2024-07-18 02:23 6.9K 
[ ]large-stack.ll2023-07-21 02:22 6.9K 
[ ]add-before-shl.ll2024-07-18 02:23 6.9K 
[ ]usub_sat_plus.ll2024-07-18 02:23 6.9K 
[ ]switch-width.ll2024-07-18 02:23 6.8K 
[ ]float-zfa.ll2024-07-18 02:23 6.8K 
[ ]inline-asm.ll2024-07-18 02:23 6.7K 
[ ]shift-masked-shamt.ll2024-07-18 02:23 6.6K 
[ ]add-imm.ll2024-07-18 02:23 6.6K 
[ ]shl-demanded.ll2024-07-18 02:23 6.5K 
[ ]rv32zbkb.ll2024-07-18 02:23 6.5K 
[ ]bswap-shift.ll2023-07-21 02:22 6.5K 
[ ]rv64zfh-half-convert-strict.ll2024-07-18 02:23 6.5K 
[ ]bfloat-mem.ll2024-07-18 02:23 6.5K 
[ ]narrow-shl-cst.ll2023-07-21 02:22 6.4K 
[ ]double-imm.ll2024-07-18 02:23 6.4K 
[ ]machinelicm-address-pseudos.ll2024-07-18 02:23 6.3K 
[ ]early-clobber-tied-def-subreg-liveness.ll2024-07-18 02:23 6.3K 
[ ]split-store.ll2024-07-18 02:23 6.3K 
[ ]half-maximum-minimum.ll2024-07-18 02:23 6.3K 
[ ]double-bitmanip-dagcombines.ll2024-07-18 02:23 6.1K 
[ ]bfloat-select-icmp.ll2024-07-18 02:23 6.0K 
[ ]xcvbitmanip.ll2024-07-18 02:23 5.9K 
[ ]intrinsic-cttz-elts-vscale.ll2024-07-18 02:23 5.9K 
[ ]rv64i-shift-sext.ll2024-07-18 02:23 5.9K 
[ ]rv64i-demanded-bits.ll2024-07-18 02:23 5.9K 
[ ]cm_mvas_mvsa.ll2024-07-18 02:23 5.9K 
[ ]and.ll2024-07-18 02:23 5.8K 
[ ]uadd_sat.ll2023-07-21 02:22 5.8K 
[ ]atomic-rmw-sub.ll2024-07-18 02:23 5.8K 
[ ]select-constant-xor.ll2023-07-21 02:22 5.8K 
[ ]xtheadmac.ll2024-07-18 02:23 5.7K 
[ ]split-offsets.ll2024-07-18 02:23 5.7K 
[ ]branch-on-zero.ll2024-07-18 02:23 5.6K 
[ ]machine-outliner-and-machine-copy-propagation.ll2024-07-18 02:23 5.6K 
[ ]shrinkwrap.ll2024-07-18 02:23 5.5K 
[ ]half-zfa-fli.ll2024-07-18 02:23 5.5K 
[ ]bfloat-fcmp.ll2024-07-18 02:23 5.5K 
[ ]riscv-codegenprepare.ll2024-07-18 02:23 5.5K 
[ ]machine-combiner-mir.ll2023-07-21 02:22 5.4K 
[ ]compress.ll2024-07-18 02:23 5.4K 
[ ]usub_sat.ll2023-07-21 02:22 5.3K 
[ ]zdinx-boundary-check.ll2024-07-18 02:23 5.3K 
[ ]shadowcallstack.ll2024-07-18 02:23 5.3K 
[ ]vararg-ilp32e.ll2024-07-18 02:23 5.3K 
[ ]riscv-codegenprepare-asm.ll2024-07-18 02:23 5.2K 
[ ]inline-asm-zfh-constraint-f.ll2024-07-18 02:23 5.1K 
[ ]zfh-half-intrinsics.ll2024-07-18 02:23 5.1K 
[ ]codemodel-lowering.ll2024-07-18 02:23 5.0K 
[ ]double-stack-spill-restore.ll2024-07-18 02:23 5.0K 
[ ]xtheadfmemidx.ll2024-07-18 02:23 5.0K 
[ ]half-imm.ll2024-07-18 02:23 5.0K 
[ ]frameaddr-returnaddr.ll2024-07-18 02:23 4.9K 
[ ]stack-realignment-with-variable-sized-objects.ll2024-07-18 02:23 4.9K 
[ ]fp16-promote.ll2024-07-18 02:23 4.9K 
[ ]bf16-promote.ll2024-07-18 02:23 4.8K 
[ ]float-bitmanip-dagcombines.ll2024-07-18 02:23 4.8K 
[ ]zfhmin-half-intrinsics.ll2024-07-18 02:23 4.7K 
[ ]half-frem.ll2024-07-18 02:23 4.7K 
[ ]bitextract-mac.ll2024-07-18 02:23 4.7K 
[ ]rv64d-double-convert-strict.ll2023-07-21 02:22 4.7K 
[ ]rv64f-float-convert-strict.ll2023-07-21 02:22 4.6K 
[ ]emutls.ll2024-07-18 02:23 4.4K 
[ ]umulo-128-legalisation-lowering.ll2024-07-18 02:23 4.3K 
[ ]float-select-verify.ll2024-07-18 02:23 4.3K 
[ ]ghccc-rv64.ll2024-07-18 02:23 4.3K 
[ ]ghccc-rv32.ll2024-07-18 02:23 4.3K 
[ ]riscv-shifted-extend.ll2024-07-18 02:23 4.3K 
[ ]stack-slot-size.ll2024-07-18 02:23 4.2K 
[ ]sifive7-enable-intervals.mir2024-07-18 02:23 4.2K 
[ ]half-zfa.ll2024-07-18 02:23 4.1K 
[ ]frm-dependency.ll2023-07-21 02:22 4.1K 
[ ]machine-outliner-cfi.mir2024-07-18 02:23 4.0K 
[ ]spill-fpr-scalar.ll2024-07-18 02:23 4.0K 
[ ]compress-float.ll2024-07-18 02:23 4.0K 
[ ]machine-outliner-position.mir2024-07-18 02:23 3.9K 
[ ]select-to-and-zext.ll2024-07-18 02:23 3.9K 
[ ]machineoutliner.mir2024-07-18 02:23 3.8K 
[ ]O0-pipeline.ll2024-07-18 02:23 3.7K 
[ ]zfhmin-imm.ll2024-07-18 02:23 3.6K 
[ ]branch.ll2024-07-18 02:23 3.5K 
[ ]exception-pointer-register.ll2024-07-18 02:23 3.5K 
[ ]macro-fusions.mir2024-07-18 02:23 3.5K 
[ ]machine-combiner-strategies.ll2024-07-18 02:23 3.4K 
[ ]aext-to-sext.ll2024-07-18 02:23 3.4K 
[ ]branch-opt.ll2024-07-18 02:23 3.4K 
[ ]reduce-unnecessary-extension.ll2024-07-18 02:23 3.4K 
[ ]alloca.ll2024-07-18 02:23 3.3K 
[ ]target-abi-invalid.ll2023-07-06 06:03 3.3K 
[ ]machine-combiner.mir2024-07-18 02:23 3.3K 
[ ]inline-asm-d-constraint-f.ll2024-07-18 02:23 3.3K 
[ ]unroll-loop-cse.ll2024-07-18 02:23 3.2K 
[ ]out-of-reach-emergency-slot.mir2024-07-18 02:23 3.2K 
[ ]intrinsic-cttz-elts.ll2024-07-18 02:23 3.2K 
[ ]calling-conv-rv32f-ilp32e.ll2024-07-18 02:23 3.2K 
[ ]local-stack-slot-allocation.ll2024-07-18 02:23 3.1K 
[ ]rv64d-double-convert.ll2023-07-21 02:22 3.1K 
[ ]live-sp.mir2024-07-18 02:23 3.1K 
[ ]mir-target-flags.ll2024-07-18 02:23 3.1K 
[ ]rv32zknh-intrinsic.ll2024-07-18 02:23 3.1K 
[ ]pr63816.ll2024-07-18 02:23 3.1K 
[ ]fp128.ll2024-07-18 02:23 3.0K 
[ ]miss-sp-restore-eh.ll2024-07-18 02:23 3.0K 
[ ]double-previous-failure.ll2024-07-18 02:23 3.0K 
[ ]reduction-formation.ll2024-07-18 02:23 3.0K 
[ ]fpenv.ll2023-07-21 02:22 2.9K 
[ ]shift-and.ll2023-07-21 02:22 2.9K 
[ ]loop-strength-reduce-loop-invar.ll2023-07-21 02:22 2.9K 
[ ]rv32i-rv64i-float-double.ll2024-07-18 02:23 2.9K 
[ ]rv64i-w-insts-legalization.ll2024-07-18 02:23 2.8K 
[ ]rv32i-rv64i-half.ll2024-07-18 02:23 2.8K 
[ ]addcarry.ll2023-07-21 02:22 2.8K 
[ ]zfbfmin.ll2024-07-18 02:23 2.8K 
[ ]inline-asm-f-constraint-f.ll2024-07-18 02:23 2.8K 
[ ]calling-conv-rv32f-ilp32.ll2024-07-18 02:23 2.7K 
[ ]interrupt-attr-callee.ll2024-07-18 02:23 2.7K 
[ ]vector-abi.ll2024-07-18 02:23 2.7K 
[ ]half-isnan.ll2024-07-18 02:23 2.7K 
[ ]zcmp-with-float.ll2024-07-18 02:23 2.6K 
[ ]shrinkwrap-jump-table.ll2024-07-18 02:23 2.6K 
[ ]atomic-fence.ll2024-07-18 02:23 2.6K 
[ ]fastcc-int.ll2024-07-18 02:23 2.6K 
[ ]loop-strength-reduce-add-cheaper-than-mul.ll2023-07-21 02:22 2.6K 
[ ]opt-w-instrs.mir2024-07-18 02:23 2.5K 
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[ ]calling-conv-vector-float.ll2024-07-18 02:23 2.0K 
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[ ]pr51206.ll2024-07-18 02:23 2.0K 
[ ]zcb-regalloc-hints.ll2024-07-18 02:23 2.0K 
[ ]kcfi-mir.ll2024-07-18 02:23 2.0K 
[ ]rv64zbkb-intrinsic.ll2024-07-18 02:23 2.0K 
[ ]global-merge-offset.ll2023-07-21 02:22 2.0K 
[ ]pr58511.ll2024-07-18 02:23 2.0K 
[ ]kcfi.ll2024-07-18 02:23 2.0K 
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[ ]fixups-diff.ll2024-07-18 02:23 1.7K 
[ ]fold-binop-into-select.ll2024-07-18 02:23 1.7K 
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[ ]rv32zbkb-intrinsic.ll2023-07-06 06:03 1.5K 
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[ ]MachineSink-implicit-x0.mir2023-07-06 06:03 935  
[ ]rv32zbc-zbkc-intrinsic.ll2023-07-21 02:22 930  
[ ]readcyclecounter.ll2023-07-06 06:03 914  
[ ]bfloat-isnan.ll2024-07-18 02:23 909  
[ ]rv64-patchpoint.ll2024-07-18 02:23 908  
[ ]select-bare.ll2023-07-21 02:22 905  
[ ]pr68855.ll2024-07-18 02:23 903  
[ ]module-target-abi2.ll2023-07-21 02:22 881  
[ ]pr66603.ll2024-07-18 02:23 861  
[ ]indirectbr.ll2023-07-21 02:22 860  
[ ]addc-adde-sube-subc.ll2023-07-06 06:03 855  
[ ]rv64zksed-intrinsic.ll2024-07-18 02:23 839  
[ ]wide-mem.ll2023-07-21 02:22 833  
[ ]pr53662.mir2023-07-21 02:22 823  
[ ]trunc-free.ll2023-07-21 02:22 813  
[ ]module-target-abi.ll2024-07-18 02:23 813  
[ ]rv32zkne-intrinsic.ll2024-07-18 02:23 808  
[ ]rv32zknd-intrinsic.ll2024-07-18 02:23 808  
[ ]rv64zksed-intrinsic-autoupgrade2.ll2024-07-18 02:23 807  
[ ]rv32zkne-intrinsic-autoupgrade.ll2024-07-18 02:23 804  
[ ]rv32zknd-intrinsic-autoupgrade.ll2024-07-18 02:23 804  
[ ]rv64zksed-intrinsic-autoupgrade.ll2024-07-18 02:23 803  
[ ]rv32zksed-intrinsic-autoupgrade.ll2024-07-18 02:23 803  
[ ]rv32zksed-intrinsic.ll2024-07-18 02:23 791  
[ ]blockaddress.ll2023-07-21 02:22 789  
[ ]align.ll2024-07-18 02:23 778  
[ ]rv64zkne-intrinsic.ll2023-07-21 02:22 768  
[ ]musttail-call.ll2023-07-21 02:22 760  
[ ]and-add-lsr.ll2024-07-18 02:23 753  
[ ]rv64zksh-intrinsic.ll2024-07-18 02:23 749  
[ ]subtarget-features-std-ext.ll2024-07-18 02:23 738  
[ ]rv64e.ll2024-07-18 02:23 737  
[ ]rv32e.ll2024-07-18 02:23 737  
[ ]pr56110.ll2024-07-18 02:23 721  
[ ]pr64503.ll2024-07-18 02:23 719  
[ ]rv64zksh-intrinsic-autoupgrade.ll2024-07-18 02:23 717  
[ ]rv32zksh-intrinsic.ll2024-07-18 02:23 701  
[ ]pr40333.ll2023-07-06 06:03 700  
[ ]rv64zbkx-intrinsic.ll2023-07-21 02:22 693  
[ ]rv32zbkx-intrinsic.ll2023-07-21 02:22 693  
[ ]pr63365.ll2024-07-18 02:23 688  
[ ]pr90652.ll2024-07-18 02:23 634  
[ ]flt-rounds.ll2023-07-21 02:22 616  
[ ]dso_local_equivalent.ll2024-07-18 02:23 603  
[ ]aext.ll2024-07-18 02:23 601  
[ ]pr58025.ll2023-07-21 02:22 593  
[ ]overflow-intrinsic-optimizations.ll2023-07-21 02:22 574  
[ ]option-nopic.ll2024-07-18 02:23 559  
[ ]pr64935.ll2024-07-18 02:23 556  
[ ]isel-optnone.ll2023-07-21 02:22 555  
[ ]rv64-stackmap-nops.ll2024-07-18 02:23 544  
[ ]pr64772.ll2024-07-18 02:23 544  
[ ]sdata-local-sym.ll2024-07-18 02:23 535  
[ ]ghccc-nest.ll2023-07-21 02:22 517  
[ ]sdata-limit-4.ll2024-07-18 02:23 516  
[ ]optnone-store-no-combine.ll2023-07-21 02:22 516  
[ ]sdata-limit-8.ll2024-07-18 02:23 506  
[ ]option-pic.ll2024-07-18 02:23 506  
[ ]sdata-limit-0.ll2024-07-18 02:23 504  
[ ]option-rvc.ll2024-07-18 02:23 489  
[ ]option-norvc.ll2023-07-06 06:03 489  
[ ]rv32zbc-intrinsic.ll2023-07-21 02:22 481  
[ ]idiv_large.ll2023-07-21 02:22 474  
[ ]pr55201.ll2023-07-21 02:22 458  
[ ]spir-kernel-cc.ll2024-07-18 02:23 443  
[ ]option-relax.ll2023-07-06 06:03 443  
[ ]option-norelax.ll2023-07-06 06:03 443  
[ ]compress-inline-asm.ll2024-07-18 02:23 427  
[ ]thread-pointer.ll2023-07-21 02:22 413  
[ ]inline-asm-i-constraint-i1.ll2023-07-06 06:03 385  
[ ]inline-option-directive.ll2024-07-18 02:23 371  
[ ]graalcc.ll2024-07-18 02:23 362  
[ ]interrupt-attr-ret-error.ll2024-07-18 02:23 357  
[ ]interrupt-attr-args-error.ll2024-07-18 02:23 355  
[ ]interrupt-attr-invalid.ll2023-07-06 06:03 334  
[ ]get-register-invalid.ll2023-07-06 06:03 307  
[ ]verify-instr.mir2024-07-18 02:23 264  
[ ]module-target-abi3.ll2023-07-21 02:22 232  
[ ]rv32-fuchsia.ll2024-07-18 02:23 187  
[ ]lit.local.cfg2024-07-18 02:23 69  
[DIR]rvv/2024-07-18 02:23 -  
[DIR]rv64-legal-i32/2024-07-18 02:23 -  
[DIR]intrinsics/2023-07-06 06:03 -  
[DIR]GlobalISel/2024-07-18 02:23 -  
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