Index of /~tb-builder/tor-browser-build/git_clones/llvm-project/llvm/test/CodeGen/Hexagon

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[ ]64bit_tstbit.ll2025-07-15 07:15 1.1K 
[ ]Atomics.ll2025-07-15 07:15 2.7K 
[ ]BranchPredict.ll2025-07-15 07:15 2.5K 
[ ]Halide_vec_cast_trunc1.ll2025-07-15 07:15 3.5K 
[ ]Halide_vec_cast_trunc2.ll2025-07-15 07:15 4.1K 
[ ]M4_mpyri_addi_global.ll2025-07-15 07:15 475  
[ ]M4_mpyrr_addi_global.ll2025-07-15 07:15 618  
[ ]NVJumpCmp.ll2025-07-15 07:15 3.9K 
[ ]P08214.ll2025-07-15 07:15 6.9K 
[ ]PR33749.ll2025-07-15 07:15 1.6K 
[ ]S3_2op.ll2025-07-15 07:15 10K 
[ ]SUnit-boundary-prob.ll2025-07-15 07:15 9.7K 
[ ]V60-VDblNew.ll2025-07-15 07:15 972  
[ ]abi-padding-2.ll2025-07-15 07:15 1.2K 
[ ]abi-padding.ll2025-07-15 07:15 1.5K 
[ ]abs.ll2025-07-15 07:15 1.7K 
[ ]absaddr-store.ll2025-07-15 07:15 1.2K 
[ ]absimm.ll2025-07-15 07:15 512  
[ ]add-use.ll2025-07-15 07:15 682  
[ ]add_int_double.ll2025-07-15 07:15 299  
[ ]add_mpi_RRR.ll2025-07-15 07:15 1.1K 
[ ]addaddi.ll2025-07-15 07:15 334  
[ ]addasl-address.ll2025-07-15 07:15 844  
[ ]addh-sext-trunc.ll2025-07-15 07:15 803  
[ ]addh-shifted.ll2025-07-15 07:15 736  
[ ]addh.ll2025-07-15 07:15 823  
[ ]addr-calc-opt.ll2025-07-15 07:15 2.3K 
[ ]addr-mode-opt.ll2025-07-15 07:15 1.7K 
[ ]addrmode-align.ll2025-07-15 07:15 1.8K 
[ ]addrmode-globoff.mir2025-07-15 07:15 438  
[ ]addrmode-immop.mir2025-07-15 07:15 1.5K 
[ ]addrmode-indoff.ll2025-07-15 07:15 2.3K 
[ ]addrmode-keepdeadphis.ll2025-07-15 07:15 1.8K 
[ ]addrmode-keepdeadphis.mir2025-07-15 07:15 559  
[ ]addrmode-neg-offset.ll2025-07-15 07:15 229  
[ ]addrmode-no-rdef.mir2025-07-15 07:15 1.2K 
[ ]addrmode-offset.ll2025-07-15 07:15 2.1K 
[ ]addrmode-opt-assert.mir2025-07-15 07:15 733  
[ ]addrmode-rr-to-io.mir2025-07-15 07:15 487  
[ ]addrspacecast-crash.ll2025-07-15 07:15 312  
[ ]addsat.ll2025-07-15 07:15 6.4K 
[ ]addsubcarry.ll2025-07-15 07:15 642  
[ ]adjust-latency-stackST.ll2025-07-15 07:15 2.6K 
[ ]aggr-antidep-tied.ll2025-07-15 07:15 1.7K 
[ ]aggr-copy-order.ll2025-07-15 07:15 1.6K 
[ ]aggr-licm.ll2025-07-15 07:15 6.4K 
[ ]aggressive_licm.ll2025-07-15 07:15 2.2K 
[ ]align_Os.ll2025-07-15 07:15 445  
[ ]align_test.ll2025-07-15 07:15 2.2K 
[ ]alu64.ll2025-07-15 07:15 15K 
[ ]always-ext.ll2025-07-15 07:15 1.5K 
[ ]anti-dep-partial.mir2025-07-15 07:15 1.1K 
[ ]arg-copy-elison.ll2025-07-15 07:15 1.6K 
[ ]args.ll2025-07-15 07:15 352  
[ ]ashift-left-right.ll2025-07-15 07:15 418  
[ ]asr-rnd.ll2025-07-15 07:15 1.4K 
[ ]asr-rnd64.ll2025-07-15 07:15 1.4K 
[ ]assert-postinc-ptr-not-value.ll2025-07-15 07:15 7.2K 
[ ]atomic-opaque-basic.ll2025-07-15 07:15 3.1K 
[ ]atomic-rmw-add.ll2025-07-15 07:15 505  
[ ]atomic-store-byte.ll2025-07-15 07:15 519  
[ ]atomicrmw-cond-sub-clamp.ll2025-07-15 07:15 9.5K 
[ ]atomicrmw-uinc-udec-wrap.ll2025-07-15 07:15 11K 
[DIR]autohvx/2025-07-15 07:15 -  
[ ]avoid-predspill-calleesaved.ll2025-07-15 07:15 1.5K 
[ ]avoid-predspill.ll2025-07-15 07:15 1.2K 
[ ]avoidVectorLowering.ll2025-07-15 07:15 557  
[ ]bank-conflict-load.mir2025-07-15 07:15 700  
[ ]bank-conflict.mir2025-07-15 07:15 5.7K 
[ ]barrier-flag.ll2025-07-15 07:15 5.5K 
[ ]base-offset-addr.ll2025-07-15 07:15 570  
[ ]base-offset-post.ll2025-07-15 07:15 1.2K 
[ ]base-offset-stv4.ll2025-07-15 07:15 892  
[ ]bit-addr-align.mir2025-07-15 07:15 471  
[ ]bit-bitsplit-at.ll2025-07-15 07:15 934  
[ ]bit-bitsplit-regclass.ll2025-07-15 07:15 1.4K 
[ ]bit-bitsplit-src.ll2025-07-15 07:15 1.1K 
[ ]bit-bitsplit.ll2025-07-15 07:15 513  
[ ]bit-cmp0.mir2025-07-15 07:15 3.8K 
[ ]bit-eval.ll2025-07-15 07:15 1.2K 
[ ]bit-ext-sat.ll2025-07-15 07:15 1.4K 
[ ]bit-extract-off.ll2025-07-15 07:15 837  
[ ]bit-extract.ll2025-07-15 07:15 1.5K 
[ ]bit-extractu-half.ll2025-07-15 07:15 343  
[ ]bit-gen-rseq.ll2025-07-15 07:15 2.0K 
[ ]bit-has.ll2025-07-15 07:15 1.8K 
[ ]bit-loop-rc-mismatch.ll2025-07-15 07:15 1.8K 
[ ]bit-loop.ll2025-07-15 07:15 4.0K 
[ ]bit-phi.ll2025-07-15 07:15 2.2K 
[ ]bit-rie.ll2025-07-15 07:15 9.5K 
[ ]bit-skip-byval.ll2025-07-15 07:15 244  
[ ]bit-store-upper-sub-hi.mir2025-07-15 07:15 657  
[ ]bit-validate-reg.ll2025-07-15 07:15 622  
[ ]bit-visit-flowq.ll2025-07-15 07:15 1.3K 
[ ]bitcast-i32-to-v32i1.ll2025-07-15 07:15 718  
[ ]bitcast-i128-to-v128i1.ll2025-07-15 07:15 1.8K 
[ ]bitcast-v2i16-to-v32i1.ll2025-07-15 07:15 588  
[ ]bitcast-v4i8-to-v32i1.ll2025-07-15 07:15 585  
[ ]bitconvert-vector.ll2025-07-15 07:15 1.0K 
[ ]bitmanip.ll2025-07-15 07:15 9.3K 
[ ]bittracker-regclass.ll2025-07-15 07:15 2.0K 
[ ]bkfir.ll2025-07-15 07:15 3.7K 
[ ]block-addr.ll2025-07-15 07:15 1.6K 
[ ]block-address.ll2025-07-15 07:15 1.0K 
[ ]block-ranges-nodef.ll2025-07-15 07:15 1.7K 
[ ]blockaddr-fpic.ll2025-07-15 07:15 7.5K 
[ ]branch-folder-hoist-kills.mir2025-07-15 07:15 1.7K 
[ ]branch-non-mbb.ll2025-07-15 07:15 1.5K 
[ ]branchfolder-insert-impdef.mir2025-07-15 07:15 2.1K 
[ ]branchfolder-keep-impdef.ll2025-07-15 07:15 901  
[ ]brcond-setne.ll2025-07-15 07:15 2.6K 
[ ]brev_ld.ll2025-07-15 07:15 3.1K 
[ ]brev_st.ll2025-07-15 07:15 3.6K 
[ ]bss-local.ll2025-07-15 07:15 642  
[ ]bug-aa4463-ifconv-vecpred.ll2025-07-15 07:15 1.6K 
[ ]bug-allocframe-size.ll2025-07-15 07:15 3.6K 
[ ]bug-hcp-tied-kill.ll2025-07-15 07:15 3.2K 
[ ]bug6757-endloop.ll2025-07-15 07:15 3.4K 
[ ]bug9049.ll2025-07-15 07:15 438  
[ ]bug9963.ll2025-07-15 07:15 320  
[ ]bug14859-iv-cleanup-lpad.ll2025-07-15 07:15 7.2K 
[ ]bug14859-split-const-block-addr.ll2025-07-15 07:15 13K 
[ ]bug15515-shuffle.ll2025-07-15 07:15 1.2K 
[ ]bug17276.ll2025-07-15 07:15 2.7K 
[ ]bug17386.ll2025-07-15 07:15 2.6K 
[ ]bug18008.ll2025-07-15 07:15 3.0K 
[ ]bug18491-optsize.ll2025-07-15 07:15 874  
[ ]bug19076.ll2025-07-15 07:15 7.0K 
[ ]bug19119.ll2025-07-15 07:15 1.6K 
[ ]bug19254-ifconv-vec.ll2025-07-15 07:15 6.0K 
[ ]bug27085.ll2025-07-15 07:15 1.3K 
[ ]bug31839.ll2025-07-15 07:15 691  
[ ]bugAsmHWloop.ll2025-07-15 07:15 2.6K 
[ ]build-attributes.ll2025-07-15 07:15 546  
[ ]build-vector-shuffle.ll2025-07-15 07:15 657  
[ ]build-vector-v4i8-zext.ll2025-07-15 07:15 1.0K 
[ ]builtin-expect.ll2025-07-15 07:15 1.3K 
[ ]builtin-prefetch-offset.ll2025-07-15 07:15 1.2K 
[ ]builtin-prefetch.ll2025-07-15 07:15 1.0K 
[ ]call-long1.ll2025-07-15 07:15 663  
[ ]call-ret-i1.ll2025-07-15 07:15 569  
[ ]call-v4.ll2025-07-15 07:15 782  
[ ]callR_noreturn.ll2025-07-15 07:15 516  
[ ]calling-conv-2.ll2025-07-15 07:15 382  
[ ]calling-conv.ll2025-07-15 07:15 1.5K 
[ ]calloperand-v2i1.ll2025-07-15 07:15 295  
[ ]calloperand-v4i1.ll2025-07-15 07:15 1.2K 
[ ]calloperand-v8i1.ll2025-07-15 07:15 1.2K 
[ ]calloperand-v16i1.ll2025-07-15 07:15 1.5K 
[ ]calloperand-v32i1.ll2025-07-15 07:15 2.1K 
[ ]calloperand-v64i1.ll2025-07-15 07:15 2.2K 
[ ]calloperand-v128i1.ll2025-07-15 07:15 1.9K 
[ ]callr-dep-edge.ll2025-07-15 07:15 426  
[ ]cext-check.ll2025-07-15 07:15 1.7K 
[ ]cext-ice.ll2025-07-15 07:15 12K 
[ ]cext-opt-basic.mir2025-07-15 07:15 1.9K 
[ ]cext-opt-block-addr.mir2025-07-15 07:15 4.9K 
[ ]cext-opt-negative-fi.mir2025-07-15 07:15 1.7K 
[ ]cext-opt-numops.mir2025-07-15 07:15 1.0K 
[ ]cext-opt-range-assert.mir2025-07-15 07:15 1.7K 
[ ]cext-opt-range-offset.mir2025-07-15 07:15 943  
[ ]cext-opt-shifted-range.mir2025-07-15 07:15 874  
[ ]cext-opt-stack-no-rr.mir2025-07-15 07:15 1.1K 
[ ]cext-unnamed-global.mir2025-07-15 07:15 1.0K 
[ ]cext-valid-packet1.ll2025-07-15 07:15 566  
[ ]cext-valid-packet2.ll2025-07-15 07:15 863  
[ ]cext.ll2025-07-15 07:15 459  
[ ]cexti16.ll2025-07-15 07:15 468  
[ ]cfgopt-fall-through.ll2025-07-15 07:15 2.0K 
[ ]cfi-late-and-regpressure-init.ll2025-07-15 07:15 2.5K 
[ ]cfi-late.ll2025-07-15 07:15 2.5K 
[ ]cfi-offset.ll2025-07-15 07:15 1.6K 
[ ]cfi_offset.ll2025-07-15 07:15 2.0K 
[ ]cfi_offset2.ll2025-07-15 07:15 3.4K 
[ ]check-dot-new.ll2025-07-15 07:15 398  
[ ]check-subregister-for-latency.ll2025-07-15 07:15 3.2K 
[ ]checktabs.ll2025-07-15 07:15 227  
[ ]circ-load-isel.ll2025-07-15 07:15 473  
[ ]circ_ld.ll2025-07-15 07:15 4.6K 
[ ]circ_ldd_bug.ll2025-07-15 07:15 13K 
[ ]circ_ldw.ll2025-07-15 07:15 526  
[ ]circ_new.ll2025-07-15 07:15 9.4K 
[ ]circ_pcr_assert.ll2025-07-15 07:15 1.2K 
[ ]circ_st.ll2025-07-15 07:15 3.6K 
[ ]clr_set_toggle.ll2025-07-15 07:15 8.3K 
[ ]cmp-extend.ll2025-07-15 07:15 1.4K 
[ ]cmp-promote.ll2025-07-15 07:15 1.6K 
[ ]cmp-to-genreg.ll2025-07-15 07:15 851  
[ ]cmp-to-predreg.ll2025-07-15 07:15 1.1K 
[ ]cmp.ll2025-07-15 07:15 4.4K 
[ ]cmp_pred.ll2025-07-15 07:15 2.7K 
[ ]cmp_pred2.ll2025-07-15 07:15 1.9K 
[ ]cmp_pred_reg.ll2025-07-15 07:15 2.7K 
[ ]cmpb-dec-imm.ll2025-07-15 07:15 895  
[ ]cmpb-eq.ll2025-07-15 07:15 2.1K 
[ ]cmpb_gtu.ll2025-07-15 07:15 3.8K 
[ ]cmpb_pred.ll2025-07-15 07:15 1.9K 
[ ]cmpbeq.ll2025-07-15 07:15 746  
[ ]cmph-gtu.ll2025-07-15 07:15 1.1K 
[ ]cmpy-round.ll2025-07-15 07:15 1.5K 
[ ]coalesce_tfri.ll2025-07-15 07:15 3.0K 
[ ]coalescing-hvx-across-calls.ll2025-07-15 07:15 1.1K 
[ ]combine-imm-ext.ll2025-07-15 07:15 353  
[ ]combine-imm-ext2.ll2025-07-15 07:15 362  
[ ]combine.ll2025-07-15 07:15 477  
[ ]combine_ir.ll2025-07-15 07:15 854  
[ ]combine_lh.ll2025-07-15 07:15 300  
[ ]combiner-lts.ll2025-07-15 07:15 2.0K 
[ ]common-gep-basic.ll2025-07-15 07:15 1.1K 
[ ]common-gep-icm.ll2025-07-15 07:15 3.1K 
[ ]common-gep-inbounds.ll2025-07-15 07:15 532  
[ ]common-global-addr.ll2025-07-15 07:15 436  
[ ]compound.ll2025-07-15 07:15 346  
[ ]concat-vectors-legalize.ll2025-07-15 07:15 41K 
[ ]const-combine.ll2025-07-15 07:15 1.4K 
[ ]const-pool-tf.ll2025-07-15 07:15 1.5K 
[ ]constant_compound.ll2025-07-15 07:15 1.7K 
[ ]constext-call.ll2025-07-15 07:15 1.6K 
[ ]constext-immstore.ll2025-07-15 07:15 6.3K 
[ ]constext-replace.ll2025-07-15 07:15 6.0K 
[ ]constp-andir-global.mir2025-07-15 07:15 549  
[ ]constp-clb.ll2025-07-15 07:15 498  
[ ]constp-combine-neg.ll2025-07-15 07:15 1.1K 
[ ]constp-ctb.ll2025-07-15 07:15 626  
[ ]constp-extract.ll2025-07-15 07:15 1.0K 
[ ]constp-physreg.ll2025-07-15 07:15 901  
[ ]constp-rewrite-branches.ll2025-07-15 07:15 408  
[ ]constp-rseq.ll2025-07-15 07:15 411  
[ ]constp-vsplat.ll2025-07-15 07:15 391  
[ ]convert-to-dot-old.ll2025-07-15 07:15 5.0K 
[ ]convert_const_i1_to_i8.ll2025-07-15 07:15 1.9K 
[ ]convertdptoint.ll2025-07-15 07:15 885  
[ ]convertdptoll.ll2025-07-15 07:15 917  
[ ]convertsptoint.ll2025-07-15 07:15 857  
[ ]convertsptoll.ll2025-07-15 07:15 898  
[ ]copy-to-combine-const64.mir2025-07-15 07:15 1.0K 
[ ]copy-to-combine-dbg.ll2025-07-15 07:15 1.9K 
[ ]count_0s.ll2025-07-15 07:15 1.2K 
[ ]countbits-basic.ll2025-07-15 07:15 1.6K 
[ ]csr-func-usedef.ll2025-07-15 07:15 2.9K 
[ ]csr-stubs-spill-threshold.ll2025-07-15 07:15 1.3K 
[ ]csr_stub_calls_dwarf_frame_info.ll2025-07-15 07:15 510  
[ ]ctor.ll2025-07-15 07:15 480  
[ ]dadd.ll2025-07-15 07:15 570  
[ ]dag-combine-select-or0.ll2025-07-15 07:15 768  
[ ]dag-indexed.ll2025-07-15 07:15 1.3K 
[ ]dccleana.ll2025-07-15 07:15 343  
[ ]dead-store-stack.ll2025-07-15 07:15 3.3K 
[ ]dealloc-store.ll2025-07-15 07:15 2.4K 
[ ]dealloc_return.ll2025-07-15 07:15 644  
[ ]debug-line_table_start.ll2025-07-15 07:15 1.2K 
[ ]debug-prologue-loc.ll2025-07-15 07:15 3.2K 
[ ]debug-prologue.ll2025-07-15 07:15 3.1K 
[ ]def-undef-deps.ll2025-07-15 07:15 2.5K 
[ ]default-align.ll2025-07-15 07:15 2.0K 
[ ]deflate.ll2025-07-15 07:15 906  
[ ]df-min-max.ll2025-07-15 07:15 1.6K 
[ ]dfp.ll2025-07-15 07:15 447  
[ ]dhry.ll2025-07-15 07:15 1.1K 
[ ]dhry_proc8.ll2025-07-15 07:15 1.6K 
[ ]dhry_stall.ll2025-07-15 07:15 1.6K 
[ ]disable-const64-tinycore.ll2025-07-15 07:15 5.1K 
[ ]disable-const64.ll2025-07-15 07:15 1.0K 
[ ]dmul.ll2025-07-15 07:15 574  
[ ]dont_rotate_pregs_at_O2.ll2025-07-15 07:15 721  
[ ]double.ll2025-07-15 07:15 686  
[ ]dsub.ll2025-07-15 07:15 574  
[ ]dualstore.ll2025-07-15 07:15 296  
[ ]duplex-addi-global-imm.mir2025-07-15 07:15 318  
[ ]duplex.ll2025-07-15 07:15 149  
[ ]dwarf-discriminator.ll2025-07-15 07:15 2.6K 
[ ]early-if-conv-lifetime.mir2025-07-15 07:15 1.8K 
[ ]early-if-conversion-bug1.ll2025-07-15 07:15 18K 
[ ]early-if-debug.mir2025-07-15 07:15 1.2K 
[ ]early-if-low8.mir2025-07-15 07:15 780  
[ ]early-if-merge-loop.ll2025-07-15 07:15 3.2K 
[ ]early-if-phi-i1.ll2025-07-15 07:15 430  
[ ]early-if-predicator-reg-killed-everywhere.mir2025-07-15 07:15 1.6K 
[ ]early-if-predicator.mir2025-07-15 07:15 2.1K 
[ ]early-if-spare.ll2025-07-15 07:15 1.9K 
[ ]early-if-vecpi.ll2025-07-15 07:15 2.5K 
[ ]early-if-vecpred.ll2025-07-15 07:15 1.2K 
[ ]early-if.ll2025-07-15 07:15 3.1K 
[ ]eh_return-r30.ll2025-07-15 07:15 377  
[ ]eh_return.ll2025-07-15 07:15 1.4K 
[ ]eh_save_restore.ll2025-07-15 07:15 2.8K 
[ ]ehabi.ll2025-07-15 07:15 2.1K 
[ ]eliminate-pred-spill.ll2025-07-15 07:15 10K 
[ ]entryBB-isLoopHdr.ll2025-07-15 07:15 1.1K 
[ ]expand-condsets-basic.ll2025-07-15 07:15 246  
[ ]expand-condsets-copy-lis.ll2025-07-15 07:15 1.2K 
[ ]expand-condsets-dead-bad.ll2025-07-15 07:15 1.5K 
[ ]expand-condsets-dead-pred.ll2025-07-15 07:15 1.5K 
[ ]expand-condsets-dead.ll2025-07-15 07:15 1.5K 
[ ]expand-condsets-def-undef.mir2025-07-15 07:15 1.2K 
[ ]expand-condsets-extend.ll2025-07-15 07:15 4.2K 
[ ]expand-condsets-imm.mir2025-07-15 07:15 473  
[ ]expand-condsets-impuse.mir2025-07-15 07:15 1.8K 
[ ]expand-condsets-impuse2.mir2025-07-15 07:15 633  
[ ]expand-condsets-phys-reg.mir2025-07-15 07:15 776  
[ ]expand-condsets-pred-undef.ll2025-07-15 07:15 636  
[ ]expand-condsets-pred-undef2.ll2025-07-15 07:15 311  
[ ]expand-condsets-rm-reg.mir2025-07-15 07:15 1.2K 
[ ]expand-condsets-rm-segment.ll2025-07-15 07:15 4.5K 
[ ]expand-condsets-same-inputs.mir2025-07-15 07:15 742  
[ ]expand-condsets-undef.ll2025-07-15 07:15 719  
[ ]expand-condsets-undef2.ll2025-07-15 07:15 1.1K 
[ ]expand-condsets-undefvni.ll2025-07-15 07:15 1.4K 
[ ]expand-condsets.ll2025-07-15 07:15 4.0K 
[ ]expand-copyw-undef.mir2025-07-15 07:15 346  
[ ]expand-vselect-kill.mir2025-07-15 07:15 320  
[ ]expand-vstorerw-undef.ll2025-07-15 07:15 3.9K 
[ ]expand-vstorerw-undef2.ll2025-07-15 07:15 13K 
[ ]expand-wselect.mir2025-07-15 07:15 354  
[ ]extload-combine.ll2025-07-15 07:15 2.0K 
[ ]extlow.ll2025-07-15 07:15 337  
[ ]extract-basic.ll2025-07-15 07:15 1.9K 
[ ]extract_0bits.ll2025-07-15 07:15 385  
[ ]extractu_0bits.ll2025-07-15 07:15 387  
[ ]fadd.ll2025-07-15 07:15 581  
[ ]fast-math-libcalls.ll2025-07-15 07:15 11K 
[ ]fcmp-nan.ll2025-07-15 07:15 4.6K 
[ ]fcmp.ll2025-07-15 07:15 1.0K 
[ ]feature-compound.ll2025-07-15 07:15 581  
[ ]feature-memops.ll2025-07-15 07:15 486  
[ ]find-loop-instr.ll2025-07-15 07:15 2.4K 
[ ]find-loop.ll2025-07-15 07:15 1.8K 
[ ]fixed-spill-mutable.ll2025-07-15 07:15 2.1K 
[ ]float-amode.ll2025-07-15 07:15 3.5K 
[ ]float-bitcast.ll2025-07-15 07:15 885  
[ ]float-const64-G0.ll2025-07-15 07:15 395  
[ ]float-gen-cmpop.ll2025-07-15 07:15 2.1K 
[ ]float.ll2025-07-15 07:15 652  
[ ]floatconvert-ieee-rnd-near.ll2025-07-15 07:15 652  
[ ]fltnvjump.ll2025-07-15 07:15 8.3K 
[ ]fmadd.ll2025-07-15 07:15 575  
[ ]fminmax-v67.ll2025-07-15 07:15 1.9K 
[ ]fminmax.ll2025-07-15 07:15 1.7K 
[ ]fmul-v67.ll2025-07-15 07:15 1.6K 
[ ]fmul.ll2025-07-15 07:15 601  
[ ]formal-args-i1.ll2025-07-15 07:15 589  
[ ]fp16-promote.ll2025-07-15 07:15 1.2K 
[ ]fp16.ll2025-07-15 07:15 2.3K 
[ ]fp_latency.ll2025-07-15 07:15 3.0K 
[ ]fpelim-basic.ll2025-07-15 07:15 3.0K 
[ ]frame-offset-overflow.ll2025-07-15 07:15 11K 
[ ]fsel.ll2025-07-15 07:15 476  
[ ]fsub.ll2025-07-15 07:15 586  
[ ]funnel-shift.ll2025-07-15 07:15 7.5K 
[ ]funnel-shift2.ll2025-07-15 07:15 933  
[ ]fusedandshift.ll2025-07-15 07:15 540  
[ ]generate-const-buildvector32.ll2025-07-15 07:15 253  
[ ]generic-cpu.ll2025-07-15 07:15 142  
[ ]getBlockAddress.ll2025-07-15 07:15 409  
[ ]glob-align-volatile.ll2025-07-15 07:15 484  
[ ]global-const-gep.ll2025-07-15 07:15 547  
[ ]global-ctor-pcrel.ll2025-07-15 07:15 1.0K 
[ ]global64bitbug.ll2025-07-15 07:15 1.1K 
[ ]gp-plus-offset-load.ll2025-07-15 07:15 1.6K 
[ ]gp-plus-offset-store.ll2025-07-15 07:15 1.1K 
[ ]gp-rel.ll2025-07-15 07:15 1.0K 
[ ]hasfp-crash1.ll2025-07-15 07:15 4.3K 
[ ]hasfp-crash2.ll2025-07-15 07:15 4.3K 
[ ]hello-world-v55.ll2025-07-15 07:15 358  
[ ]hello-world-v60.ll2025-07-15 07:15 358  
[ ]hexagon-cond-jumpr31.ll2025-07-15 07:15 646  
[ ]hexagon-copy-hoisting.mir2025-07-15 07:15 1.2K 
[ ]hexagon-strcpy.ll2025-07-15 07:15 2.1K 
[ ]hexagon-tfr-add.ll2025-07-15 07:15 7.0K 
[ ]hexagon-verify-implicit-use.ll2025-07-15 07:15 1.4K 
[ ]hexagon_cfi_offset.ll2025-07-15 07:15 3.9K 
[ ]hexagon_vector_loop_carried_reuse.ll2025-07-15 07:15 4.3K 
[ ]hexagon_vector_loop_carried_reuse_commutative.ll2025-07-15 07:15 3.3K 
[ ]hexagon_vector_loop_carried_reuse_constant.ll2025-07-15 07:15 4.3K 
[ ]hexagon_vector_loop_carried_reuse_invalid.ll2025-07-15 07:15 1.4K 
[ ]hidden-relocation.ll2025-07-15 07:15 631  
[ ]honor-optsize.ll2025-07-15 07:15 1.2K 
[ ]hrc-stack-coloring.ll2025-07-15 07:15 28K 
[ ]hvx-bitcast-v64i1.ll2025-07-15 07:15 2.4K 
[ ]hvx-byte-store-double.ll2025-07-15 07:15 2.1K 
[ ]hvx-byte-store.ll2025-07-15 07:15 2.1K 
[ ]hvx-concat-lower.ll2025-07-15 07:15 6.5K 
[ ]hvx-dbl-dual-output.ll2025-07-15 07:15 3.1K 
[ ]hvx-double-vzero.ll2025-07-15 07:15 937  
[ ]hvx-dual-output.ll2025-07-15 07:15 3.0K 
[ ]hvx-isel-vselect-v256i16.ll2025-07-15 07:15 4.9K 
[ ]hvx-loopidiom-memcpy.ll2025-07-15 07:15 1.0K 
[ ]hvx-nontemporal.ll2025-07-15 07:15 1.0K 
[ ]hvx-reuse-fi-base.ll2025-07-15 07:15 7.9K 
[ ]hvx-vzero.ll2025-07-15 07:15 917  
[ ]hwloop-cleanup.ll2025-07-15 07:15 2.6K 
[ ]hwloop-const.ll2025-07-15 07:15 816  
[ ]hwloop-crit-edge.ll2025-07-15 07:15 2.2K 
[ ]hwloop-dbg-register.mir2025-07-15 07:15 4.3K 
[ ]hwloop-dbg.ll2025-07-15 07:15 3.1K 
[ ]hwloop-dist-check.mir2025-07-15 07:15 9.2K 
[ ]hwloop-ice.ll2025-07-15 07:15 497  
[ ]hwloop-le.ll2025-07-15 07:15 11K 
[ ]hwloop-long.ll2025-07-15 07:15 1.9K 
[ ]hwloop-loop1.ll2025-07-15 07:15 2.3K 
[ ]hwloop-lt.ll2025-07-15 07:15 10K 
[ ]hwloop-lt1.ll2025-07-15 07:15 1.3K 
[ ]hwloop-missed.ll2025-07-15 07:15 1.5K 
[ ]hwloop-ne.ll2025-07-15 07:15 11K 
[ ]hwloop-noreturn-call.ll2025-07-15 07:15 1.5K 
[ ]hwloop-ph-deadcode.ll2025-07-15 07:15 555  
[ ]hwloop-phi-subreg.ll2025-07-15 07:15 1.9K 
[ ]hwloop-pos-ivbump1.ll2025-07-15 07:15 1.4K 
[ ]hwloop-preh.ll2025-07-15 07:15 1.8K 
[ ]hwloop-preheader.ll2025-07-15 07:15 1.5K 
[ ]hwloop-range.ll2025-07-15 07:15 1.0K 
[ ]hwloop-recursion.ll2025-07-15 07:15 1.6K 
[ ]hwloop-redef-imm.mir2025-07-15 07:15 1.5K 
[ ]hwloop-subreg.ll2025-07-15 07:15 784  
[ ]hwloop-swap.ll2025-07-15 07:15 774  
[ ]hwloop-with-return-call.ll2025-07-15 07:15 828  
[ ]hwloop-wrap.ll2025-07-15 07:15 613  
[ ]hwloop-wrap2.ll2025-07-15 07:15 2.2K 
[ ]hwloop1.ll2025-07-15 07:15 4.4K 
[ ]hwloop2.ll2025-07-15 07:15 1.1K 
[ ]hwloop3.ll2025-07-15 07:15 716  
[ ]hwloop4.ll2025-07-15 07:15 2.9K 
[ ]hwloop5.ll2025-07-15 07:15 3.7K 
[ ]hx_V6_lo_hi.ll2025-07-15 07:15 2.3K 
[ ]i1_VarArg.ll2025-07-15 07:15 1.1K 
[ ]i8_VarArg.ll2025-07-15 07:15 916  
[ ]i16_VarArg.ll2025-07-15 07:15 918  
[ ]i128-bitop.ll2025-07-15 07:15 3.0K 
[ ]i128-fpconv-strict.ll2025-07-15 07:15 3.2K 
[ ]idxload-with-zero-offset.ll2025-07-15 07:15 1.8K 
[ ]ifcvt-common-kill.mir2025-07-15 07:15 942  
[ ]ifcvt-diamond-bad.ll2025-07-15 07:15 1.4K 
[ ]ifcvt-diamond-bug-2016-08-26.ll2025-07-15 07:15 1.4K 
[ ]ifcvt-diamond-ret.mir2025-07-15 07:15 696  
[ ]ifcvt-edge-weight.ll2025-07-15 07:15 1.4K 
[ ]ifcvt-impuse-livein.mir2025-07-15 07:15 1.0K 
[ ]ifcvt-live-subreg.mir2025-07-15 07:15 1.2K 
[ ]ifcvt-simple-bprob.ll2025-07-15 07:15 734  
[ ]ignore-terminal-mbb.ll2025-07-15 07:15 806  
[ ]imm-range-check.ll2025-07-15 07:15 1.0K 
[ ]indirect-br.ll2025-07-15 07:15 265  
[ ]infinite-loop.ll2025-07-15 07:15 1.4K 
[ ]initial-exec.ll2025-07-15 07:15 382  
[ ]inline-asm-a.ll2025-07-15 07:15 425  
[ ]inline-asm-bad-constraint.ll2025-07-15 07:15 550  
[ ]inline-asm-clobber-lr.ll2025-07-15 07:15 563  
[ ]inline-asm-error.ll2025-07-15 07:15 433  
[ ]inline-asm-filetype-null.ll2025-07-15 07:15 136  
[ ]inline-asm-hexagon.ll2025-07-15 07:15 1.0K 
[ ]inline-asm-i1.ll2025-07-15 07:15 424  
[ ]inline-asm-qv.ll2025-07-15 07:15 758  
[ ]inline-asm-vecpred128.ll2025-07-15 07:15 475  
[ ]inline-division-space.ll2025-07-15 07:15 775  
[ ]inline-division.ll2025-07-15 07:15 726  
[ ]inlineasm-output-template.ll2025-07-15 07:15 833  
[ ]insert-basic.ll2025-07-15 07:15 2.1K 
[ ]insert.ll2025-07-15 07:15 2.0K 
[ ]insert4.ll2025-07-15 07:15 5.3K 
[ ]instrprof-custom.ll2025-07-15 07:15 770  
[ ]intrinsics-v60-alu.ll2025-07-15 07:15 38K 
[ ]intrinsics-v60-misc.ll2025-07-15 07:15 22K 
[ ]intrinsics-v60-permute.ll2025-07-15 07:15 5.4K 
[ ]intrinsics-v60-shift.ll2025-07-15 07:15 1.7K 
[ ]intrinsics-v60-vcmp.ll2025-07-15 07:15 16K 
[ ]intrinsics-v60-vmpy-acc-128B.ll2025-07-15 07:15 17K 
[ ]intrinsics-v60-vmpy-acc.ll2025-07-15 07:15 17K 
[ ]intrinsics-v60-vmpy.ll2025-07-15 07:15 18K 
[ ]intrinsics-v66.ll2025-07-15 07:15 1.3K 
[ ]intrinsics-v67.ll2025-07-15 07:15 8.4K 
[DIR]intrinsics/2025-07-15 07:15 -  
[ ]invalid-dotnew-attempt.mir2025-07-15 07:15 379  
[ ]invalid-memrefs.ll2025-07-15 07:15 3.1K 
[ ]is-legal-void.ll2025-07-15 07:15 1.7K 
[ ]isel-bitcast-v1i8-i8.ll2025-07-15 07:15 626  
[ ]isel-bitcast-v8i1-i8.ll2025-07-15 07:15 436  
[ ]isel-bitcast-v8i8-v4i16.ll2025-07-15 07:15 420  
[ ]isel-buildvector-v2f16.ll2025-07-15 07:15 3.7K 
[ ]isel-combine-half.ll2025-07-15 07:15 926  
[ ]isel-dcfetch-intrin-map.ll2025-07-15 07:15 363  
[ ]isel-exti1.ll2025-07-15 07:15 502  
[ ]isel-extload-i1.ll2025-07-15 07:15 929  
[ ]isel-extract-pred.ll2025-07-15 07:15 1.8K 
[ ]isel-fold-shl-zext.ll2025-07-15 07:15 1.3K 
[ ]isel-global-offset-alignment.ll2025-07-15 07:15 1.5K 
[ ]isel-hvx-pred-bitcast-order.ll2025-07-15 07:15 768  
[ ]isel-i1arg-crash.ll2025-07-15 07:15 111  
[ ]isel-insert-pred.ll2025-07-15 07:15 2.7K 
[ ]isel-memory-vNi1.ll2025-07-15 07:15 6.6K 
[ ]isel-minmax-v64bit.ll2025-07-15 07:15 5.5K 
[ ]isel-op-zext-i1.ll2025-07-15 07:15 448  
[ ]isel-prefer.ll2025-07-15 07:15 3.0K 
[ ]isel-select-v4i8.ll2025-07-15 07:15 1.3K 
[ ]isel-setcc-i1.ll2025-07-15 07:15 680  
[ ]isel-setcc-legalize-loop.ll2025-07-15 07:15 689  
[ ]isel-simplify-crash.ll2025-07-15 07:15 1.6K 
[ ]isel-splat-vector-crash.ll2025-07-15 07:15 1.7K 
[ ]isel-splat-vector-dag-crash.ll2025-07-15 07:15 1.6K 
[ ]isel-splat-vector-neg-i8.ll2025-07-15 07:15 492  
[ ]isel-store-rr-i1.ll2025-07-15 07:15 403  
[ ]isel-uaddo-1-i64.ll2025-07-15 07:15 330  
[ ]isel-uaddo-1.ll2025-07-15 07:15 1.1K 
[ ]isel-v3i16.ll2025-07-15 07:15 1.2K 
[ ]isel-vacopy.ll2025-07-15 07:15 387  
[ ]isel-vlsr-v2i16.ll2025-07-15 07:15 428  
[ ]isel-vselect-v4i8.ll2025-07-15 07:15 293  
[ ]isel-zext-vNi1.ll2025-07-15 07:15 2.2K 
[DIR]isel/2025-07-15 07:15 -  
[ ]iss127296.ll2025-07-15 07:15 578  
[ ]jt-in-text.ll2025-07-15 07:15 2.3K 
[ ]jump-prob.ll2025-07-15 07:15 7.9K 
[ ]jump-table-g0.ll2025-07-15 07:15 1.0K 
[ ]jump-table-isel.ll2025-07-15 07:15 3.0K 
[ ]large-number-of-preds.ll2025-07-15 07:15 12K 
[ ]late-pred.ll2025-07-15 07:15 720  
[ ]late_instr.ll2025-07-15 07:15 9.3K 
[ ]lcomm.ll2025-07-15 07:15 278  
[ ]ldst_vector_offset.ll2025-07-15 07:15 2.9K 
[ ]lit.local.cfg2025-07-15 07:15 71  
[ ]livephysregs-add-pristines.mir2025-07-15 07:15 1.1K 
[ ]livephysregs-lane-masks.mir2025-07-15 07:15 1.0K 
[ ]livephysregs-lane-masks2.mir2025-07-15 07:15 1.4K 
[ ]livephysregs-regmask-clobber.mir2025-07-15 07:15 1.8K 
[ ]llvm.exp10.ll2025-07-15 07:15 6.6K 
[ ]llvm.frexp.ll2025-07-15 07:15 25K 
[ ]llvm.sincos.ll2025-07-15 07:15 43K 
[ ]load-abs.ll2025-07-15 07:15 2.5K 
[ ]load-const-extend-opt.ll2025-07-15 07:15 2.3K 
[ ]load-widen.ll2025-07-15 07:15 1.2K 
[ ]loadi1-G0.ll2025-07-15 07:15 771  
[ ]loadi1-v4-G0.ll2025-07-15 07:15 755  
[ ]loadi1-v4.ll2025-07-15 07:15 763  
[ ]loadi1.ll2025-07-15 07:15 779  
[ ]local-exec.ll2025-07-15 07:15 590  
[ ]long-calls.ll2025-07-15 07:15 2.0K 
[ ]loop-balign.ll2025-07-15 07:15 4.2K 
[DIR]loop-idiom/2025-07-15 07:15 -  
[ ]loop-prefetch.ll2025-07-15 07:15 1.1K 
[ ]loop-rotate-bug.ll2025-07-15 07:15 2.6K 
[ ]loop-rotate-liveins.ll2025-07-15 07:15 2.9K 
[ ]loopIdiom.ll2025-07-15 07:15 2.6K 
[ ]loop_align_count.ll2025-07-15 07:15 5.7K 
[ ]loop_align_count.mir2025-07-15 07:15 6.0K 
[ ]loop_correctness.ll2025-07-15 07:15 5.5K 
[ ]lower-extract-subvector.ll2025-07-15 07:15 1.3K 
[ ]lower-i1.ll2025-07-15 07:15 255  
[ ]lsr-post-inc-cross-use-offsets.ll2025-07-15 07:15 13K 
[ ]lsr-postinc-nested-loop.ll2025-07-15 07:15 2.7K 
[ ]machine-cp-clobbers.mir2025-07-15 07:15 1.2K 
[ ]machine-sink-float-usr.mir2025-07-15 07:15 14K 
[ ]machine-sink.ll2025-07-15 07:15 2.2K 
[ ]macint.ll2025-07-15 07:15 387  
[ ]maddsubu.ll2025-07-15 07:15 630  
[ ]mapped_intrinsics.ll2025-07-15 07:15 3.7K 
[ ]mask-instr.ll2025-07-15 07:15 1.0K 
[ ]mask.ll2025-07-15 07:15 376  
[ ]maxd.ll2025-07-15 07:15 228  
[ ]maxh.ll2025-07-15 07:15 805  
[ ]maxud.ll2025-07-15 07:15 229  
[ ]maxuw.ll2025-07-15 07:15 229  
[ ]maxw.ll2025-07-15 07:15 228  
[ ]mem-fi-add.ll2025-07-15 07:15 1.0K 
[ ]mem-load-circ.ll2025-07-15 07:15 3.2K 
[ ]mem-ops-sub.ll2025-07-15 07:15 1.1K 
[ ]mem-ops-sub_01.ll2025-07-15 07:15 1.1K 
[ ]mem-ops-sub_i16.ll2025-07-15 07:15 1.1K 
[ ]mem-ops-sub_i16_01.ll2025-07-15 07:15 1.1K 
[ ]memcmp.ll2025-07-15 07:15 1.4K 
[ ]memcpy-likely-aligned.ll2025-07-15 07:15 1.5K 
[ ]memcpy-memmove-inline.ll2025-07-15 07:15 1.5K 
[ ]memop-bit18.ll2025-07-15 07:15 528  
[ ]memops-stack.ll2025-07-15 07:15 4.5K 
[ ]memops.ll2025-07-15 07:15 45K 
[ ]memops1.ll2025-07-15 07:15 1.0K 
[ ]memops2.ll2025-07-15 07:15 830  
[ ]memops3.ll2025-07-15 07:15 812  
[ ]memops_global.ll2025-07-15 07:15 18K 
[ ]memset-inline.ll2025-07-15 07:15 641  
[ ]mind.ll2025-07-15 07:15 228  
[ ]minu-zext-8.ll2025-07-15 07:15 315  
[ ]minu-zext-16.ll2025-07-15 07:15 326  
[ ]minud.ll2025-07-15 07:15 229  
[ ]minuw.ll2025-07-15 07:15 229  
[ ]minw.ll2025-07-15 07:15 228  
[ ]mipi-double-small.ll2025-07-15 07:15 756  
[ ]misaligned-access.ll2025-07-15 07:15 422  
[ ]misaligned-const-load.ll2025-07-15 07:15 1.6K 
[ ]misaligned-const-store.ll2025-07-15 07:15 1.6K 
[ ]misaligned_double_vector_store_not_fast.ll2025-07-15 07:15 2.9K 
[ ]misched-top-rptracker-sync.ll2025-07-15 07:15 7.4K 
[ ]mlong-calls.ll2025-07-15 07:15 918  
[ ]mnaci_v66.ll2025-07-15 07:15 505  
[ ]mpy.ll2025-07-15 07:15 569  
[ ]mpysin-imm.ll2025-07-15 07:15 429  
[ ]mul64-sext.ll2025-07-15 07:15 2.6K 
[ ]mul64.ll2025-07-15 07:15 6.3K 
[ ]mulh.ll2025-07-15 07:15 583  
[ ]mulhs.ll2025-07-15 07:15 685  
[ ]multi-cycle.ll2025-07-15 07:15 4.6K 
[ ]mux-basic.ll2025-07-15 07:15 958  
[ ]mux-kill1.mir2025-07-15 07:15 315  
[ ]mux-kill2.mir2025-07-15 07:15 443  
[ ]mux-kill3.mir2025-07-15 07:15 1.0K 
[ ]mux-undef.ll2025-07-15 07:15 650  
[ ]muxii-bug.ll2025-07-15 07:15 844  
[ ]muxii-crash.ll2025-07-15 07:15 405  
[ ]naked-fn-with-frame-pointer.ll2025-07-15 07:15 836  
[ ]namedreg.ll2025-07-15 07:15 649  
[ ]nbench1.ll2025-07-15 07:15 2.4K 
[ ]neg.ll2025-07-15 07:15 340  
[ ]newify-crash.ll2025-07-15 07:15 1.8K 
[ ]newvalueSameReg.ll2025-07-15 07:15 2.1K 
[ ]newvaluejump-c4.mir2025-07-15 07:15 921  
[ ]newvaluejump-float.mir2025-07-15 07:15 439  
[ ]newvaluejump-kill.ll2025-07-15 07:15 1.7K 
[ ]newvaluejump-kill2.mir2025-07-15 07:15 493  
[ ]newvaluejump-postinc.ll2025-07-15 07:15 3.2K 
[ ]newvaluejump-solo.mir2025-07-15 07:15 408  
[ ]newvaluejump.ll2025-07-15 07:15 936  
[ ]newvaluejump2.ll2025-07-15 07:15 743  
[ ]newvaluejump3.ll2025-07-15 07:15 2.6K 
[ ]newvaluestore.ll2025-07-15 07:15 310  
[ ]newvaluestore2.ll2025-07-15 07:15 671  
[ ]no-falign-function-for-size.ll2025-07-15 07:15 208  
[ ]no-packets-gather.ll2025-07-15 07:15 1.4K 
[ ]no-packets.ll2025-07-15 07:15 2.1K 
[ ]noFalignAfterCallAtO2.ll2025-07-15 07:15 1.5K 
[ ]no_struct_element.ll2025-07-15 07:15 865  
[ ]noreturn-noepilog.ll2025-07-15 07:15 756  
[ ]noreturn-notail.ll2025-07-15 07:15 782  
[ ]noreturn-stack-elim.ll2025-07-15 07:15 2.6K 
[ ]not-op.ll2025-07-15 07:15 293  
[ ]notcheap.ll2025-07-15 07:15 1.9K 
[ ]ntstbit.ll2025-07-15 07:15 1.7K 
[ ]nv_store_vec.ll2025-07-15 07:15 723  
[ ]opt-addr-mode-subreg-use.ll2025-07-15 07:15 6.6K 
[ ]opt-addr-mode.ll2025-07-15 07:15 4.4K 
[ ]opt-fabs.ll2025-07-15 07:15 434  
[ ]opt-fneg.ll2025-07-15 07:15 968  
[ ]opt-glob-addrs-000.ll2025-07-15 07:15 5.1K 
[ ]opt-glob-addrs-001.ll2025-07-15 07:15 7.6K 
[ ]opt-glob-addrs-003.ll2025-07-15 07:15 19K 
[ ]opt-sext-intrinsics.ll2025-07-15 07:15 802  
[ ]opt-spill-volatile.ll2025-07-15 07:15 784  
[ ]optimize-mux.ll2025-07-15 07:15 580  
[ ]order-stack-object.ll2025-07-15 07:15 6.2K 
[ ]packed-store.ll2025-07-15 07:15 1.5K 
[ ]packetize-allocframe.ll2025-07-15 07:15 1.8K 
[ ]packetize-call-r29.ll2025-07-15 07:15 578  
[ ]packetize-cfi-location.ll2025-07-15 07:15 1.9K 
[ ]packetize-dccleana.mir2025-07-15 07:15 438  
[ ]packetize-debug-loc.mir2025-07-15 07:15 2.0K 
[ ]packetize-frame-setup-destroy.mir2025-07-15 07:15 1.5K 
[ ]packetize-impdef-1.ll2025-07-15 07:15 4.6K 
[ ]packetize-impdef.ll2025-07-15 07:15 7.9K 
[ ]packetize-l2fetch.ll2025-07-15 07:15 1.2K 
[ ]packetize-load-store-aliasing.mir2025-07-15 07:15 1.1K 
[ ]packetize-nvj-no-prune.mir2025-07-15 07:15 820  
[ ]packetize-nvstore.mir2025-07-15 07:15 645  
[ ]packetize-return-arg.ll2025-07-15 07:15 1.1K 
[ ]packetize-tailcall-arg.ll2025-07-15 07:15 416  
[ ]packetize-update-offset.mir2025-07-15 07:15 903  
[ ]packetize-vgather-slot01.mir2025-07-15 07:15 647  
[ ]packetize-volatiles.ll2025-07-15 07:15 847  
[ ]packetize_cond_inst.ll2025-07-15 07:15 895  
[ ]packetizer-resources.ll2025-07-15 07:15 839  
[ ]partword-cmpxchg.ll2025-07-15 07:15 658  
[ ]peephole-kill-flags.ll2025-07-15 07:15 693  
[ ]peephole-move-phi.ll2025-07-15 07:15 2.2K 
[ ]peephole-op-swap.ll2025-07-15 07:15 1.1K 
[ ]phi-elim.ll2025-07-15 07:15 683  
[ ]pic-jt-big.ll2025-07-15 07:15 2.1K 
[ ]pic-jumptables.ll2025-07-15 07:15 1.4K 
[ ]pic-local.ll2025-07-15 07:15 324  
[ ]pic-regusage.ll2025-07-15 07:15 3.1K 
[ ]pic-sdata.ll2025-07-15 07:15 1.1K 
[ ]pic-simple.ll2025-07-15 07:15 603  
[ ]pic-static.ll2025-07-15 07:15 610  
[DIR]pipeliner/2025-07-15 07:15 -  
[ ]plt-rel.ll2025-07-15 07:15 1.3K 
[ ]pmpyw_acc.ll2025-07-15 07:15 1.6K 
[ ]post-inc-aa-metadata.ll2025-07-15 07:15 1.5K 
[ ]post-ra-kill-update.mir2025-07-15 07:15 1.0K 
[ ]postinc-aggr-dag-cycle.ll2025-07-15 07:15 3.2K 
[ ]postinc-baseoffset.mir2025-07-15 07:15 643  
[ ]postinc-float.ll2025-07-15 07:15 2.7K 
[ ]postinc-load.ll2025-07-15 07:15 947  
[ ]postinc-offset.ll2025-07-15 07:15 1.3K 
[ ]postinc-order.ll2025-07-15 07:15 2.1K 
[ ]postinc-store.ll2025-07-15 07:15 935  
[ ]postra-sink-subregs.mir2025-07-15 07:15 1.1K 
[ ]pred-absolute-store.ll2025-07-15 07:15 435  
[ ]pred-gp.ll2025-07-15 07:15 904  
[ ]pred-instrs.ll2025-07-15 07:15 934  
[ ]pred-sched.ll2025-07-15 07:15 1.1K 
[ ]pred-simp.ll2025-07-15 07:15 683  
[ ]pred-taken-jump.ll2025-07-15 07:15 1.5K 
[ ]predicate-copy.ll2025-07-15 07:15 486  
[ ]predicate-logical.ll2025-07-15 07:15 1.1K 
[ ]predicate-rcmp.ll2025-07-15 07:15 692  
[ ]predtfrs.ll2025-07-15 07:15 1.8K 
[ ]prefetch-intr.ll2025-07-15 07:15 552  
[ ]prefetch-shuffler-ice.ll2025-07-15 07:15 586  
[ ]prob-types.ll2025-07-15 07:15 5.4K 
[ ]prof-early-if.ll2025-07-15 07:15 3.0K 
[ ]propagate-vcombine.ll2025-07-15 07:15 1.9K 
[ ]ps_call_nr.ll2025-07-15 07:15 1.2K 
[ ]rdf-copy-clobber.mir2025-07-15 07:15 5.2K 
[ ]rdf-copy-renamable-reserved.mir2025-07-15 07:15 438  
[ ]rdf-copy-undef.ll2025-07-15 07:15 5.3K 
[ ]rdf-copy-undef2.ll2025-07-15 07:15 2.6K 
[ ]rdf-copy.ll2025-07-15 07:15 1.7K 
[ ]rdf-cover-use.ll2025-07-15 07:15 1.2K 
[ ]rdf-dce-double-cover.mir2025-07-15 07:15 1.8K 
[ ]rdf-dead-loop.ll2025-07-15 07:15 1.0K 
[ ]rdf-def-mask.ll2025-07-15 07:15 1.8K 
[ ]rdf-ehlabel-live.mir2025-07-15 07:15 321  
[ ]rdf-extra-livein.ll2025-07-15 07:15 2.4K 
[ ]rdf-filter-defs.ll2025-07-15 07:15 4.9K 
[ ]rdf-ignore-undef.ll2025-07-15 07:15 1.9K 
[ ]rdf-inline-asm-fixed.ll2025-07-15 07:15 1.5K 
[ ]rdf-inline-asm.ll2025-07-15 07:15 1.3K 
[ ]rdf-kill-last-op.ll2025-07-15 07:15 7.0K 
[ ]rdf-multiple-phis-up.ll2025-07-15 07:15 1.1K 
[ ]rdf-phi-clobber.mir2025-07-15 07:15 3.0K 
[ ]rdf-phi-shadows.ll2025-07-15 07:15 2.4K 
[ ]rdf-phi-up.ll2025-07-15 07:15 1.9K 
[ ]rdf-reset-kills.ll2025-07-15 07:15 819  
[ ]readcyclecounter.ll2025-07-15 07:15 252  
[ ]readsteadycounter.ll2025-07-15 07:15 257  
[ ]redundant-branching2.ll2025-07-15 07:15 2.1K 
[ ]reg-by-name.ll2025-07-15 07:15 19K 
[ ]reg-eq-cmp.ll2025-07-15 07:15 1.1K 
[ ]reg-scav-imp-use-dbl-vec.ll2025-07-15 07:15 13K 
[ ]reg-scavengebug-2.ll2025-07-15 07:15 6.4K 
[ ]reg-scavengebug-3.ll2025-07-15 07:15 3.9K 
[ ]reg-scavengebug-4.ll2025-07-15 07:15 11K 
[ ]reg-scavengebug-5.ll2025-07-15 07:15 15K 
[ ]reg-scavengebug.ll2025-07-15 07:15 12K 
[ ]reg-scavenger-valid-slot.ll2025-07-15 07:15 22K 
[ ]reg_seq.ll2025-07-15 07:15 3.8K 
[ ]regalloc-bad-undef.mir2025-07-15 07:15 19K 
[ ]regalloc-block-overlap.ll2025-07-15 07:15 5.3K 
[ ]regalloc-coal-extend-short-subrange.mir2025-07-15 07:15 1.3K 
[ ]regalloc-coal-fullreg-undef.mir2025-07-15 07:15 1.1K 
[ ]regalloc-liveout-undef.mir2025-07-15 07:15 972  
[ ]registerpassbuildercallbacks.ll2025-07-15 07:15 933  
[ ]registerscav-missing-spill-slot.ll2025-07-15 07:15 6.8K 
[ ]registerscavenger-fail1.ll2025-07-15 07:15 10K 
[ ]regp-underflow.ll2025-07-15 07:15 5.5K 
[ ]regscav-wrong-super-sub-regs.ll2025-07-15 07:15 7.3K 
[ ]regscavenger_fail_hwloop.ll2025-07-15 07:15 13K 
[ ]regscavengerbug.ll2025-07-15 07:15 19K 
[ ]relax.ll2025-07-15 07:15 284  
[ ]remove-endloop.ll2025-07-15 07:15 1.8K 
[ ]remove_lsr.ll2025-07-15 07:15 2.4K 
[ ]restore-single-reg.ll2025-07-15 07:15 1.2K 
[ ]ret-struct-by-val.ll2025-07-15 07:15 346  
[ ]retval-redundant-copy.ll2025-07-15 07:15 467  
[ ]rotate-multi.ll2025-07-15 07:15 2.3K 
[ ]rotate.ll2025-07-15 07:15 4.4K 
[ ]rotl-i64.ll2025-07-15 07:15 602  
[ ]runtime-stkchk.ll2025-07-15 07:15 1.7K 
[ ]save-kill-csr.ll2025-07-15 07:15 3.4K 
[ ]save-regs-thresh.ll2025-07-15 07:15 3.3K 
[ ]sdata-array.ll2025-07-15 07:15 238  
[ ]sdata-basic.ll2025-07-15 07:15 437  
[ ]sdata-expand-const.ll2025-07-15 07:15 473  
[ ]sdata-explicit-section.ll2025-07-15 07:15 246  
[ ]sdata-load-size.ll2025-07-15 07:15 513  
[ ]sdata-opaque-type.ll2025-07-15 07:15 263  
[ ]sdata-stack-guard.ll2025-07-15 07:15 1.8K 
[ ]sdiv-minsigned.ll2025-07-15 07:15 399  
[ ]sdr-basic.ll2025-07-15 07:15 532  
[ ]sdr-global.mir2025-07-15 07:15 510  
[ ]sdr-nosplit1.ll2025-07-15 07:15 1.5K 
[ ]sdr-reg-profit.ll2025-07-15 07:15 3.5K 
[ ]sdr-shr32.ll2025-07-15 07:15 777  
[ ]section_7275.ll2025-07-15 07:15 1.5K 
[ ]select-instr-align.ll2025-07-15 07:15 860  
[ ]select-vector-pred.ll2025-07-15 07:15 1.3K 
[ ]setmemrefs.ll2025-07-15 07:15 874  
[ ]sf-min-max.ll2025-07-15 07:15 1.5K 
[ ]sffms.ll2025-07-15 07:15 814  
[ ]sfmin_dce.ll2025-07-15 07:15 442  
[ ]sfmpyacc_scale.ll2025-07-15 07:15 914  
[ ]shrink-frame-basic.ll2025-07-15 07:15 1.0K 
[ ]signed_immediates.ll2025-07-15 07:15 1.7K 
[ ]signext-inreg.ll2025-07-15 07:15 9.4K 
[ ]simple-types-mem.ll2025-07-15 07:15 507  
[ ]simple_addend.ll2025-07-15 07:15 240  
[ ]simpletailcall.ll2025-07-15 07:15 316  
[ ]simplify64bitops_7223.ll2025-07-15 07:15 1.7K 
[ ]spill-vector-alignment.mir2025-07-15 07:15 484  
[ ]split-const32-const64.ll2025-07-15 07:15 723  
[ ]split-muxii.ll2025-07-15 07:15 634  
[ ]split-vecpred.ll2025-07-15 07:15 4.1K 
[ ]stack-align-reset.ll2025-07-15 07:15 1.6K 
[ ]stack-align1.ll2025-07-15 07:15 399  
[ ]stack-align2.ll2025-07-15 07:15 536  
[ ]stack-alloca1.ll2025-07-15 07:15 347  
[ ]stack-alloca2.ll2025-07-15 07:15 478  
[ ]stack-guard-acceptable-type.ll2025-07-15 07:15 1.0K 
[ ]static.ll2025-07-15 07:15 462  
[ ]store-AbsSet.ll2025-07-15 07:15 2.2K 
[ ]store-abs.ll2025-07-15 07:15 1.8K 
[ ]store-const-extend-opt.ll2025-07-15 07:15 2.6K 
[ ]store-constant.ll2025-07-15 07:15 1.0K 
[ ]store-imm-amode.ll2025-07-15 07:15 3.6K 
[ ]store-imm-byte.ll2025-07-15 07:15 238  
[ ]store-imm-halword.ll2025-07-15 07:15 239  
[ ]store-imm-large-stack.ll2025-07-15 07:15 11K 
[ ]store-imm-stack-object.ll2025-07-15 07:15 2.6K 
[ ]store-imm-word.ll2025-07-15 07:15 239  
[ ]store-shift.ll2025-07-15 07:15 1.9K 
[ ]store-vector-pred.ll2025-07-15 07:15 3.2K 
[ ]store-widen-aliased-load.ll2025-07-15 07:15 479  
[ ]store-widen-negv.ll2025-07-15 07:15 368  
[ ]store-widen-negv2.ll2025-07-15 07:15 472  
[ ]store-widen-subreg.ll2025-07-15 07:15 2.2K 
[ ]store-widen.ll2025-07-15 07:15 606  
[ ]store1.ll2025-07-15 07:15 968  
[ ]store_abs.ll2025-07-15 07:15 719  
[ ]storerd-io-over-rr.ll2025-07-15 07:15 330  
[ ]storerinewabs.ll2025-07-15 07:15 400  
[ ]struct-const.ll2025-07-15 07:15 2.0K 
[ ]struct_args.ll2025-07-15 07:15 337  
[ ]struct_args_large.ll2025-07-15 07:15 398  
[ ]struct_copy.ll2025-07-15 07:15 2.1K 
[ ]struct_copy_sched_r16.ll2025-07-15 07:15 798  
[ ]sub-add.ll2025-07-15 07:15 3.0K 
[ ]subh-shifted.ll2025-07-15 07:15 693  
[ ]subh.ll2025-07-15 07:15 688  
[ ]subi-asl.ll2025-07-15 07:15 1.7K 
[ ]switch-lut-explicit-section.ll2025-07-15 07:15 1.7K 
[ ]switch-lut-function-section.ll2025-07-15 07:15 1.6K 
[ ]switch-lut-multiple-functions.ll2025-07-15 07:15 2.0K 
[ ]switch-lut-text-section.ll2025-07-15 07:15 1.5K 
[ ]swp-alias-cross-iteration.mir2025-07-15 07:15 2.5K 
[ ]swp-art-deps-rec.ll2025-07-15 07:15 5.5K 
[ ]swp-bad-sched.ll2025-07-15 07:15 5.3K 
[ ]swp-badorder.ll2025-07-15 07:15 1.1K 
[ ]swp-carried-1.ll2025-07-15 07:15 2.1K 
[ ]swp-carried-dep1.mir2025-07-15 07:15 3.6K 
[ ]swp-carried-dep2.mir2025-07-15 07:15 2.9K 
[ ]swp-carried-dep3.mir2025-07-15 07:15 2.3K 
[ ]swp-carried-dep4.mir2025-07-15 07:15 1.0K 
[ ]swp-carried-dep5.mir2025-07-15 07:15 5.5K 
[ ]swp-chain-refs.ll2025-07-15 07:15 2.1K 
[ ]swp-change-dep-cycle.ll2025-07-15 07:15 1.2K 
[ ]swp-change-dep.ll2025-07-15 07:15 1.9K 
[ ]swp-change-dep1.ll2025-07-15 07:15 1.4K 
[ ]swp-change-deps.ll2025-07-15 07:15 2.0K 
[ ]swp-check-offset.ll2025-07-15 07:15 1.4K 
[ ]swp-const-tc.ll2025-07-15 07:15 1.4K 
[ ]swp-const-tc1.ll2025-07-15 07:15 2.2K 
[ ]swp-const-tc2.ll2025-07-15 07:15 1.1K 
[ ]swp-const-tc3.ll2025-07-15 07:15 4.2K 
[ ]swp-conv3x3-nested.ll2025-07-15 07:15 8.9K 
[ ]swp-copytophi-dag.ll2025-07-15 07:15 3.8K 
[ ]swp-crash-iter.ll2025-07-15 07:15 1.5K 
[ ]swp-cse-phi.ll2025-07-15 07:15 1.5K 
[ ]swp-dag-phi.ll2025-07-15 07:15 1.4K 
[ ]swp-dag-phi1.ll2025-07-15 07:15 1.2K 
[ ]swp-dead-regseq.ll2025-07-15 07:15 1.2K 
[ ]swp-dep-neg-offset.ll2025-07-15 07:15 2.2K 
[ ]swp-disable-Os.ll2025-07-15 07:15 4.5K 
[ ]swp-epilog-numphis.ll2025-07-15 07:15 3.9K 
[ ]swp-epilog-phi2.ll2025-07-15 07:15 2.7K 
[ ]swp-epilog-phi4.ll2025-07-15 07:15 1.2K 
[ ]swp-epilog-phi5.ll2025-07-15 07:15 6.9K 
[ ]swp-epilog-phi6.ll2025-07-15 07:15 2.9K 
[ ]swp-epilog-phi7.ll2025-07-15 07:15 14K 
[ ]swp-epilog-phi8.ll2025-07-15 07:15 1.6K 
[ ]swp-epilog-phi9.ll2025-07-15 07:15 2.1K 
[ ]swp-epilog-phi10.ll2025-07-15 07:15 4.0K 
[ ]swp-epilog-phi11.ll2025-07-15 07:15 1.2K 
[ ]swp-epilog-phi12.ll2025-07-15 07:15 2.0K 
[ ]swp-epilog-phi13.ll2025-07-15 07:15 2.1K 
[ ]swp-epilog-reuse-1.ll2025-07-15 07:15 1.9K 
[ ]swp-epilog-reuse.ll2025-07-15 07:15 3.1K 
[ ]swp-epilog-reuse2.ll2025-07-15 07:15 2.5K 
[ ]swp-epilog-reuse3.ll2025-07-15 07:15 3.2K 
[ ]swp-epilog-reuse4.ll2025-07-15 07:15 3.8K 
[ ]swp-exit-fixup.ll2025-07-15 07:15 2.3K 
[ ]swp-fix-last-use.ll2025-07-15 07:15 947  
[ ]swp-fix-last-use1.ll2025-07-15 07:15 2.0K 
[ ]swp-intreglow8.ll2025-07-15 07:15 3.7K 
[ ]swp-kernel-last-use.ll2025-07-15 07:15 2.6K 
[ ]swp-kernel-phi1.ll2025-07-15 07:15 1.6K 
[ ]swp-large-rec.ll2025-07-15 07:15 2.5K 
[ ]swp-listen-loop3.ll2025-07-15 07:15 2.2K 
[ ]swp-loop-carried-crash.ll2025-07-15 07:15 18K 
[ ]swp-loop-carried-order-dep1.mir2025-07-15 07:15 3.5K 
[ ]swp-loop-carried-order-dep2.mir2025-07-15 07:15 3.4K 
[ ]swp-loop-carried-order-dep3.mir2025-07-15 07:15 3.7K 
[ ]swp-loop-carried-order-dep4.mir2025-07-15 07:15 3.4K 
[ ]swp-loop-carried-order-dep5.mir2025-07-15 07:15 3.6K 
[ ]swp-loop-carried-order-dep6.mir2025-07-15 07:15 5.6K 
[ ]swp-loop-carried-unknown.ll2025-07-15 07:15 1.6K 
[ ]swp-loop-carried.ll2025-07-15 07:15 1.4K 
[ ]swp-loopval.ll2025-07-15 07:15 1.8K 
[ ]swp-lots-deps.ll2025-07-15 07:15 2.0K 
[ ]swp-matmul-bitext.ll2025-07-15 07:15 2.9K 
[ ]swp-max-stage3.ll2025-07-15 07:15 1.8K 
[ ]swp-max.ll2025-07-15 07:15 1.5K 
[ ]swp-maxstart.ll2025-07-15 07:15 1.4K 
[ ]swp-memrefs-epilog.ll2025-07-15 07:15 4.5K 
[ ]swp-more-phi.ll2025-07-15 07:15 1.9K 
[ ]swp-multi-loops.ll2025-07-15 07:15 2.5K 
[ ]swp-multi-phi-refs.ll2025-07-15 07:15 2.0K 
[ ]swp-new-phi.ll2025-07-15 07:15 1.7K 
[ ]swp-no-alias.mir2025-07-15 07:15 5.6K 
[ ]swp-node-order.ll2025-07-15 07:15 1.7K 
[ ]swp-order-carried.ll2025-07-15 07:15 2.9K 
[ ]swp-order-copies.ll2025-07-15 07:15 1.2K 
[ ]swp-order-deps1.ll2025-07-15 07:15 1.4K 
[ ]swp-order-deps3.ll2025-07-15 07:15 849  
[ ]swp-order-deps4.ll2025-07-15 07:15 2.7K 
[ ]swp-order-deps5.ll2025-07-15 07:15 818  
[ ]swp-order-deps6.ll2025-07-15 07:15 828  
[ ]swp-order-deps7.ll2025-07-15 07:15 1.6K 
[ ]swp-order-prec.ll2025-07-15 07:15 919  
[ ]swp-order.ll2025-07-15 07:15 2.0K 
[ ]swp-order1.ll2025-07-15 07:15 1.1K 
[ ]swp-phi-ch-offset.ll2025-07-15 07:15 2.3K 
[ ]swp-phi-chains.ll2025-07-15 07:15 5.5K 
[ ]swp-phi-def-use.ll2025-07-15 07:15 3.9K 
[ ]swp-phi-dep.ll2025-07-15 07:15 2.2K 
[ ]swp-phi-dep1.ll2025-07-15 07:15 4.0K 
[ ]swp-phi-order.ll2025-07-15 07:15 873  
[ ]swp-phi-ref.ll2025-07-15 07:15 2.0K 
[ ]swp-phi-ref1.ll2025-07-15 07:15 2.4K 
[ ]swp-phi-start.ll2025-07-15 07:15 1.5K 
[ ]swp-phi.ll2025-07-15 07:15 6.0K 
[ ]swp-physreg.ll2025-07-15 07:15 1.5K 
[ ]swp-pragma-disable-bug.ll2025-07-15 07:15 2.6K 
[ ]swp-pragma-disable.ii2025-07-15 07:15 1.4K 
[ ]swp-pragma-initiation-interval-reset.ii2025-07-15 07:15 2.5K 
[ ]swp-pragma-initiation-interval.ii2025-07-15 07:15 1.4K 
[ ]swp-prolog-phi.ll2025-07-15 07:15 2.3K 
[ ]swp-prolog-phi4.ll2025-07-15 07:15 3.1K 
[ ]swp-regseq.ll2025-07-15 07:15 677  
[ ]swp-remove-dep-ice.ll2025-07-15 07:15 1.1K 
[ ]swp-rename-dead-phi.ll2025-07-15 07:15 2.2K 
[ ]swp-rename.ll2025-07-15 07:15 891  
[ ]swp-replace-uses1.ll2025-07-15 07:15 1.9K 
[ ]swp-resmii-1.ll2025-07-15 07:15 4.4K 
[ ]swp-resmii.ll2025-07-15 07:15 1.3K 
[ ]swp-reuse-phi-1.ll2025-07-15 07:15 1.7K 
[ ]swp-reuse-phi-2.ll2025-07-15 07:15 2.1K 
[ ]swp-reuse-phi-4.ll2025-07-15 07:15 7.1K 
[ ]swp-reuse-phi-5.ll2025-07-15 07:15 1.7K 
[ ]swp-reuse-phi-6.ll2025-07-15 07:15 5.6K 
[ ]swp-reuse-phi.ll2025-07-15 07:15 1.1K 
[ ]swp-sigma.ll2025-07-15 07:15 11K 
[ ]swp-stages.ll2025-07-15 07:15 3.0K 
[ ]swp-stages3.ll2025-07-15 07:15 2.2K 
[ ]swp-stages4.ll2025-07-15 07:15 3.5K 
[ ]swp-stages5.ll2025-07-15 07:15 2.8K 
[ ]swp-subreg.ll2025-07-15 07:15 1.1K 
[ ]swp-swap.ll2025-07-15 07:15 1.6K 
[ ]swp-tfri.ll2025-07-15 07:15 1.7K 
[ ]swp-vect-dotprod.ll2025-07-15 07:15 1.7K 
[ ]swp-vmult.ll2025-07-15 07:15 1.0K 
[ ]swp-vsum.ll2025-07-15 07:15 1.1K 
[ ]swp-ws-dead-def.mir2025-07-15 07:15 6.4K 
[ ]swp-ws-exp-dbg.mir2025-07-15 07:15 21K 
[ ]swp-ws-exp.mir2025-07-15 07:15 6.1K 
[ ]swp-ws-fail-0.mir2025-07-15 07:15 2.1K 
[ ]swp-ws-fail-1.mir2025-07-15 07:15 1.6K 
[ ]swp-ws-fail-2.mir2025-07-15 07:15 2.6K 
[ ]swp-ws-fail-3.mir2025-07-15 07:15 1.6K 
[ ]swp-ws-live-intervals-issue123165.mir2025-07-15 07:15 3.1K 
[ ]swp-ws-live-intervals-issue128714.mir2025-07-15 07:15 6.9K 
[ ]swp-ws-live-intervals.mir2025-07-15 07:15 8.7K 
[ ]swp-ws-meta-instr.mir2025-07-15 07:15 6.2K 
[ ]swp-ws-phi.mir2025-07-15 07:15 1.2K 
[ ]swp-ws-pragma-initiation-interval-fail.mir2025-07-15 07:15 2.5K 
[ ]swp-ws-resource-reserve.mir2025-07-15 07:15 4.4K 
[ ]swp-ws-sqrt.mir2025-07-15 07:15 6.4K 
[ ]swp-ws-stall-cycle.mir2025-07-15 07:15 1.8K 
[ ]swp-ws-weak-dep.mir2025-07-15 07:15 1.1K 
[ ]swp-ws-zero-cost.mir2025-07-15 07:15 1.5K 
[ ]swp-xxh2.ll2025-07-15 07:15 1.8K 
[ ]tail-call-mem-intrinsics.ll2025-07-15 07:15 1.0K 
[ ]tail-call-trunc.ll2025-07-15 07:15 553  
[ ]tail-dup-subreg-abort.ll2025-07-15 07:15 702  
[ ]tail-dup-subreg-map.ll2025-07-15 07:15 2.5K 
[ ]tailcall_fastcc_ccc.ll2025-07-15 07:15 447  
[ ]target-flag-ext.mir2025-07-15 07:15 833  
[ ]tc_duplex.ll2025-07-15 07:15 778  
[ ]tc_duplex_asm.ll2025-07-15 07:15 778  
[ ]tc_sched.ll2025-07-15 07:15 2.5K 
[ ]tc_sched1.ll2025-07-15 07:15 794  
[ ]tcm-zext.ll2025-07-15 07:15 504  
[ ]testbits.ll2025-07-15 07:15 682  
[ ]tfr-cleanup.ll2025-07-15 07:15 2.3K 
[ ]tfr-mux-nvj.ll2025-07-15 07:15 855  
[ ]tfr-slotindex.ll2025-07-15 07:15 1.0K 
[ ]tfr-to-combine.ll2025-07-15 07:15 802  
[ ]tied_oper.ll2025-07-15 07:15 1.4K 
[ ]tiny_bkfir_artdeps.ll2025-07-15 07:15 7.5K 
[ ]tiny_bkfir_loop_align.ll2025-07-15 07:15 7.6K 
[ ]tinycore.ll2025-07-15 07:15 1.7K 
[ ]tls_gd.ll2025-07-15 07:15 623  
[ ]tls_pic.ll2025-07-15 07:15 1.0K 
[ ]tls_static.ll2025-07-15 07:15 771  
[ ]trap-crash.ll2025-07-15 07:15 528  
[ ]trap-unreachable.ll2025-07-15 07:15 212  
[ ]trivialmemaliascheck.ll2025-07-15 07:15 1.4K 
[ ]trunc-mpy.ll2025-07-15 07:15 2.7K 
[ ]tstbit.ll2025-07-15 07:15 2.4K 
[ ]two-addr-tied-subregs.mir2025-07-15 07:15 1.8K 
[ ]two-crash.ll2025-07-15 07:15 928  
[ ]twoaddressbug.ll2025-07-15 07:15 4.4K 
[ ]undef-ret.ll2025-07-15 07:15 487  
[ ]undo-dag-shift.ll2025-07-15 07:15 1.6K 
[ ]union-1.ll2025-07-15 07:15 502  
[ ]unordered-fcmp.ll2025-07-15 07:15 2.0K 
[ ]unreachable-mbb-phi-subreg.mir2025-07-15 07:15 632  
[ ]upper-mpy.ll2025-07-15 07:15 3.0K 
[ ]usr-ovf-dep.ll2025-07-15 07:15 1.0K 
[ ]v5_insns.ll2025-07-15 07:15 2.5K 
[ ]v6-haar-balign32.ll2025-07-15 07:15 5.7K 
[ ]v6-inlasm1.ll2025-07-15 07:15 3.9K 
[ ]v6-inlasm2.ll2025-07-15 07:15 1.0K 
[ ]v6-inlasm3.ll2025-07-15 07:15 1.5K 
[ ]v6-inlasm4.ll2025-07-15 07:15 952  
[ ]v6-shuffl.ll2025-07-15 07:15 3.2K 
[ ]v6-spill1.ll2025-07-15 07:15 14K 
[ ]v6-unaligned-spill.ll2025-07-15 07:15 2.0K 
[ ]v6-vecpred-copy.ll2025-07-15 07:15 7.2K 
[ ]v6vassignp.ll2025-07-15 07:15 866  
[ ]v6vec-vmemcur-prob.mir2025-07-15 07:15 429  
[ ]v6vec-vmemu1.ll2025-07-15 07:15 2.3K 
[ ]v6vec-vmemu2.ll2025-07-15 07:15 913  
[ ]v6vec-vprint.ll2025-07-15 07:15 1.6K 
[ ]v6vec-vshuff.ll2025-07-15 07:15 1.1K 
[ ]v6vec_inc1.ll2025-07-15 07:15 2.6K 
[ ]v6vec_zero.ll2025-07-15 07:15 586  
[ ]v6vect-dbl-fail1.ll2025-07-15 07:15 1.3K 
[ ]v6vect-dbl-spill.ll2025-07-15 07:15 10K 
[ ]v6vect-dbl.ll2025-07-15 07:15 6.1K 
[ ]v6vect-dh1.ll2025-07-15 07:15 7.3K 
[ ]v6vect-locals1.ll2025-07-15 07:15 1.3K 
[ ]v6vect-no-sideeffects.ll2025-07-15 07:15 6.0K 
[ ]v6vect-pred2.ll2025-07-15 07:15 1.6K 
[ ]v6vect-spill-kill.ll2025-07-15 07:15 9.4K 
[ ]v6vect-vmem1.ll2025-07-15 07:15 769  
[ ]v6vect-vsplat.ll2025-07-15 07:15 2.5K 
[ ]v60-align.ll2025-07-15 07:15 1.3K 
[ ]v60-cur.ll2025-07-15 07:15 3.2K 
[ ]v60-haar-postinc.ll2025-07-15 07:15 4.5K 
[ ]v60-halide-vcombinei8.ll2025-07-15 07:15 2.6K 
[ ]v60-vec-128b-1.ll2025-07-15 07:15 1.3K 
[ ]v60-vecpred-spill.ll2025-07-15 07:15 10K 
[ ]v60-vsel1.ll2025-07-15 07:15 3.0K 
[ ]v60-vsel2.ll2025-07-15 07:15 3.6K 
[ ]v60Intrins.ll2025-07-15 07:15 156K 
[ ]v60Vasr.ll2025-07-15 07:15 12K 
[ ]v60_Q6_P_rol_PI.ll2025-07-15 07:15 801  
[ ]v60_sort16.ll2025-07-15 07:15 3.8K 
[ ]v60rol-instrs.ll2025-07-15 07:15 1.7K 
[ ]v60small.ll2025-07-15 07:15 3.0K 
[ ]v62-CJAllSlots.ll2025-07-15 07:15 2.2K 
[ ]v62-inlasm4.ll2025-07-15 07:15 898  
[ ]vacopy.ll2025-07-15 07:15 1.0K 
[ ]vadd1.ll2025-07-15 07:15 913  
[ ]vaddh.ll2025-07-15 07:15 513  
[ ]validate-offset.ll2025-07-15 07:15 1.1K 
[ ]vararg-deallocate-sp.ll2025-07-15 07:15 328  
[ ]vararg-formal.ll2025-07-15 07:15 247  
[ ]vararg-linux-abi.ll2025-07-15 07:15 3.0K 
[ ]vararg.ll2025-07-15 07:15 4.2K 
[ ]vararg_align_check.ll2025-07-15 07:15 7.2K 
[ ]vararg_double_onstack.ll2025-07-15 07:15 9.0K 
[ ]vararg_named.ll2025-07-15 07:15 8.4K 
[ ]varargs-memv.ll2025-07-15 07:15 930  
[ ]vassign-to-combine.ll2025-07-15 07:15 3.1K 
[ ]vcombine128_to_req_seq.ll2025-07-15 07:15 3.4K 
[ ]vcombine_subreg.ll2025-07-15 07:15 936  
[ ]vcombine_to_req_seq.ll2025-07-15 07:15 1.9K 
[ ]vcombine_zero_diff_ptrs.ll2025-07-15 07:15 2.2K 
[ ]vdmpy-halide-test.ll2025-07-15 07:15 9.5K 
[ ]vdotprod.ll2025-07-15 07:15 1.4K 
[ ]vec-align.ll2025-07-15 07:15 1.3K 
[ ]vec-call-full1.ll2025-07-15 07:15 1.3K 
[ ]vec-pred-spill1.ll2025-07-15 07:15 4.0K 
[ ]vec-vararg-align.ll2025-07-15 07:15 1.1K 
[ ]vecPred2Vec.ll2025-07-15 07:15 1.3K 
[ ]vect-any_extend.ll2025-07-15 07:15 389  
[ ]vect-dbl-post-inc.ll2025-07-15 07:15 1.2K 
[ ]vect-downscale.ll2025-07-15 07:15 7.1K 
[ ]vect-regpairs.ll2025-07-15 07:15 9.0K 
[ ]vect-set_cc_v2i32.ll2025-07-15 07:15 6.2K 
[ ]vect-vd0.ll2025-07-15 07:15 676  
[ ]vect-zero_extend.ll2025-07-15 07:15 653  
[DIR]vect/2025-07-15 07:15 -  
[ ]vect_setcc.ll2025-07-15 07:15 3.0K 
[ ]vect_setcc_v2i16.ll2025-07-15 07:15 3.8K 
[ ]vector-align.ll2025-07-15 07:15 1.3K 
[ ]vector-ext-load.ll2025-07-15 07:15 320  
[ ]vector-sint-to-fp.ll2025-07-15 07:15 6.4K 
[ ]vector-zext-v4i8.ll2025-07-15 07:15 6.3K 
[ ]verify-liveness-at-def.mir2025-07-15 07:15 2.5K 
[ ]verify-sink-code.ll2025-07-15 07:15 9.5K 
[ ]verify-undef.ll2025-07-15 07:15 1.1K 
[ ]vextract-basic.mir2025-07-15 07:15 715  
[ ]vgather-opt-addr.ll2025-07-15 07:15 5.3K 
[ ]vgather-packetize.mir2025-07-15 07:15 964  
[ ]vload-postinc-sel.ll2025-07-15 07:15 2.3K 
[ ]vmemu-128.ll2025-07-15 07:15 781  
[ ]vmpa-halide-test.ll2025-07-15 07:15 16K 
[ ]vpack_eo.ll2025-07-15 07:15 3.9K 
[ ]vrcmpys.ll2025-07-15 07:15 2.5K 
[ ]vselect-pseudo.ll2025-07-15 07:15 1.3K 
[ ]vsplat-ext.ll2025-07-15 07:15 795  
[ ]vsplat-isel.ll2025-07-15 07:15 241  
[ ]wcsrtomb.ll2025-07-15 07:15 5.9K 
[ ]widen-alias.ll2025-07-15 07:15 3.5K 
[ ]widen-not-load.ll2025-07-15 07:15 1.7K 
[ ]widen-volatile.ll2025-07-15 07:15 1.2K 
[ ]xray-pred-ret.ll2025-07-15 07:15 590  
[ ]xray.ll2025-07-15 07:15 1.1K 
[ ]zextloadi1.ll2025-07-15 07:15 935  
Apache Server at tb-build-06.torproject.org Port 443