Index of /~tb-builder/tor-browser-build/git_clones/llvm-project.old/llvm/lib/Target/AMDGPU

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[TXT]SIISelLowering.cpp2025-07-14 12:22 667K 
[TXT]SIInstrInfo.cpp2025-07-14 12:22 369K 
[TXT]AMDGPULegalizerInfo.cpp2025-07-14 12:22 275K 
[TXT]AMDGPUInstructionSelector.cpp2025-07-14 12:22 234K 
[TXT]AMDGPUISelLowering.cpp2025-07-14 12:22 224K 
[TXT]AMDGPURegisterBankInfo.cpp2025-07-14 12:22 209K 
[ ]BUFInstructions.td2025-07-14 12:22 152K 
[ ]FLATInstructions.td2025-07-14 12:22 149K 
[ ]SIInstructions.td2025-07-14 12:22 148K 
[TXT]SIRegisterInfo.cpp2025-07-14 12:22 148K 
[TXT]AMDGPUISelDAGToDAG.cpp2025-07-14 12:22 138K 
[ ]SIInstrInfo.td2025-07-14 12:22 131K 
[ ]VOP3PInstructions.td2025-07-14 12:22 130K 
[ ]VOP3Instructions.td2025-07-14 12:22 126K 
[ ]VOPCInstructions.td2025-07-14 12:22 123K 
[ ]SOPInstructions.td2025-07-14 12:22 120K 
[ ]VOP2Instructions.td2025-07-14 12:22 118K 
[TXT]SIInsertWaitcnts.cpp2025-07-14 12:22 109K 
[TXT]GCNHazardRecognizer.cpp2025-07-14 12:22 106K 
[TXT]SIMemoryLegalizer.cpp2025-07-14 12:22 104K 
[TXT]AMDGPULowerBufferFatPointers.cpp2025-07-14 12:22 98K 
[ ]MIMGInstructions.td2025-07-14 12:22 96K 
[TXT]SIFoldOperands.cpp2025-07-14 12:22 94K 
[TXT]AMDGPUIGroupLP.cpp2025-07-14 12:22 93K 
[TXT]SILoadStoreOptimizer.cpp2025-07-14 12:22 91K 
[ ]AMDGPU.td2025-07-14 12:22 88K 
[TXT]AMDGPUTargetMachine.cpp2025-07-14 12:22 87K 
[TXT]SIFrameLowering.cpp2025-07-14 12:22 84K 
[TXT]AMDGPUCodeGenPrepare.cpp2025-07-14 12:22 84K 
[ ]DSInstructions.td2025-07-14 12:22 82K 
[TXT]GCNSchedStrategy.cpp2025-07-14 12:22 82K 
[TXT]R600ISelLowering.cpp2025-07-14 12:22 77K 
[ ]VOPInstructions.td2025-07-14 12:22 74K 
[TXT]AMDGPUAsmPrinter.cpp2025-07-14 12:22 70K 
[ ]VOP1Instructions.td2025-07-14 12:22 70K 
[TXT]AMDGPUInstCombineIntrinsic.cpp2025-07-14 12:22 68K 
[TXT]SIMachineScheduler.cpp2025-07-14 12:22 67K 
[ ]SMInstructions.td2025-07-14 12:22 63K 
[TXT]AMDGPULowerModuleLDSPass.cpp2025-07-14 12:22 63K 
[TXT]SIWholeQuadMode.cpp2025-07-14 12:22 62K 
[TXT]AMDGPUPromoteAlloca.cpp2025-07-14 12:22 60K 
[TXT]AMDGPUCallLowering.cpp2025-07-14 12:22 60K 
[TXT]SIInstrInfo.h2025-07-14 12:22 59K 
[TXT]AMDGPUSwLowerLDS.cpp2025-07-14 12:22 57K 
[TXT]AMDGPUTargetTransformInfo.cpp2025-07-14 12:22 56K 
[TXT]AMDGPULibCalls.cpp2025-07-14 12:22 56K 
[TXT]R600MachineCFGStructurizer.cpp2025-07-14 12:22 55K 
[TXT]AMDGPUSplitModule.cpp2025-07-14 12:22 55K 
[ ]R600Instructions.td2024-07-18 02:23 55K 
[TXT]GCNSubtarget.h2025-07-14 12:22 53K 
[ ]SIRegisterInfo.td2025-07-14 12:22 52K 
[TXT]AMDGPUAttributor.cpp2025-07-14 12:22 51K 
[TXT]SIPeepholeSDWA.cpp2025-07-14 12:22 50K 
[TXT]R600InstrInfo.cpp2025-07-14 12:22 48K 
[TXT]SIFixSGPRCopies.cpp2025-07-14 12:22 42K 
[TXT]AMDGPULibFunc.cpp2025-07-14 12:22 41K 
[TXT]SIMachineFunctionInfo.h2025-07-14 12:22 39K 
[TXT]SIShrinkInstructions.cpp2025-07-14 12:22 36K 
[TXT]AMDGPUAtomicOptimizer.cpp2025-07-14 12:22 36K 
[TXT]GCNRegPressure.cpp2025-07-14 12:22 34K 
[TXT]SIDefines.h2025-07-14 12:22 34K 
[TXT]AMDGPURegBankLegalizeHelper.cpp2025-07-14 12:22 33K 
[TXT]AMDKernelCodeT.h2023-07-21 02:22 33K 
[ ]AMDGPUInstructions.td2025-07-14 12:22 30K 
[TXT]SILowerI1Copies.cpp2025-07-14 12:22 30K 
[ ]EvergreenInstructions.td2025-07-14 12:22 30K 
[TXT]SIISelLowering.h2025-07-14 12:22 30K 
[TXT]AMDGPURegBankLegalizeRules.cpp2025-07-14 12:22 29K 
[TXT]SIMachineFunctionInfo.cpp2025-07-14 12:22 29K 
[TXT]GCNDPPCombine.cpp2025-07-14 12:22 28K 
[TXT]SILowerControlFlow.cpp2025-07-14 12:22 28K 
[TXT]SIOptimizeExecMasking.cpp2025-07-14 12:22 28K 
[ ]AMDGPUSearchableTables.td2025-07-14 12:22 28K 
[TXT]AMDGPUHSAMetadataStreamer.cpp2025-07-14 12:22 27K 
[TXT]SIOptimizeVGPRLiveRange.cpp2025-07-14 12:22 26K 
[TXT]GCNSubtarget.cpp2025-07-14 12:22 24K 
[TXT]AMDGPUISelLowering.h2025-07-14 12:22 22K 
[TXT]SILowerSGPRSpills.cpp2025-07-14 12:22 22K 
[TXT]R600ControlFlowFinalizer.cpp2025-07-14 12:22 22K 
[TXT]GCNIterativeScheduler.cpp2025-07-14 12:22 22K 
[TXT]AMDGPU.h2025-07-14 12:22 20K 
[TXT]AMDGPULateCodeGenPrepare.cpp2025-07-14 12:22 20K 
[TXT]GCNRegPressure.h2025-07-14 12:22 20K 
[TXT]SIRegisterInfo.h2025-07-14 12:22 20K 
[ ]AMDGPUInstrInfo.td2025-07-14 12:22 19K 
[TXT]AMDGPUWaitSGPRHazards.cpp2025-07-14 12:22 19K 
[TXT]SIModeRegister.cpp2025-07-14 12:22 19K 
[ ]SISchedule.td2025-07-14 12:22 19K 
[TXT]AMDGPURegBankCombiner.cpp2025-07-14 12:22 19K 
[TXT]GCNSchedStrategy.h2025-07-14 12:22 19K 
[TXT]AMDGPUPostLegalizerCombiner.cpp2025-07-14 12:22 18K 
[TXT]AMDGPUResourceUsageAnalysis.cpp2025-07-14 12:22 18K 
[TXT]GCNRewritePartialRegUses.cpp2025-07-14 12:22 18K 
[TXT]AMDGPUCombinerHelper.cpp2025-07-14 12:22 18K 
[TXT]AMDGPUInsertDelayAlu.cpp2025-07-14 12:22 17K 
[TXT]AMDGPUInstructionSelector.h2025-07-14 12:22 17K 
[TXT]SIOptimizeExecMaskingPreRA.cpp2025-07-14 12:22 17K 
[TXT]AMDGPUSubtarget.cpp2025-07-14 12:22 17K 
[ ]AMDGPUGISel.td2025-07-14 12:22 16K 
[TXT]AMDGPUMCResourceInfo.cpp2025-07-14 12:22 16K 
[TXT]AMDGPUAsanInstrumentation.cpp2025-07-14 12:22 16K 
[TXT]AMDGPUPrintfRuntimeBinding.cpp2025-07-14 12:22 16K 
[TXT]SIMachineScheduler.h2025-07-14 12:22 16K 
[TXT]SIPreEmitPeephole.cpp2025-07-14 12:22 15K 
[TXT]AMDGPUPerfHintAnalysis.cpp2025-07-14 12:22 15K 
[TXT]AMDGPUMCInstLower.cpp2025-07-14 12:22 15K 
[TXT]SIFormMemoryClauses.cpp2025-07-14 12:22 14K 
[TXT]SIModeRegisterDefaults.cpp2025-07-14 12:22 14K 
[TXT]AMDGPUMemoryUtils.cpp2025-07-14 12:22 14K 
[TXT]R600InstrInfo.h2025-07-14 12:22 14K 
[TXT]SIAnnotateControlFlow.cpp2025-07-14 12:22 14K 
[TXT]AMDGPUUnifyDivergentExitNodes.cpp2025-07-14 12:22 13K 
[TXT]R600MachineScheduler.cpp2025-07-14 12:22 13K 
[TXT]R600Packetizer.cpp2025-07-14 12:22 13K 
[ ]SIInstrFormats.td2025-07-14 12:22 13K 
[TXT]AMDGPUSubtarget.h2025-07-14 12:22 13K 
[TXT]AMDGPUISelDAGToDAG.h2025-07-14 12:22 13K 
[TXT]AMDGPURegBankLegalize.cpp2025-07-14 12:22 13K 
[TXT]AMDGPURewriteOutArguments.cpp2025-07-14 12:22 13K 
[ ]VOPDInstructions.td2025-07-14 12:22 13K 
[TXT]AMDGPUTargetTransformInfo.h2025-07-14 12:22 12K 
[TXT]GCNNSAReassign.cpp2025-07-14 12:22 12K 
[TXT]AMDGPULowerKernelAttributes.cpp2025-07-14 12:22 12K 
[TXT]AMDGPUPreloadKernelArguments.cpp2025-07-14 12:22 12K 
[TXT]AMDGPUImageIntrinsicOptimizer.cpp2025-07-14 12:22 12K 
[TXT]AMDGPUGlobalISelDivergenceLowering.cpp2025-07-14 12:22 12K 
[TXT]R600OptimizeVectorRegisters.cpp2025-07-14 12:22 12K 
[TXT]AMDGPULibFunc.h2025-07-14 12:22 12K 
[TXT]AMDGPULegalizerInfo.h2025-07-14 12:22 12K 
[ ]R600InstrFormats.td2023-07-06 06:03 12K 
[TXT]R600OpenCLImageTypeLoweringPass.cpp2025-07-14 12:22 11K 
[TXT]GCNILPSched.cpp2025-07-14 12:22 11K 
[TXT]SILateBranchLowering.cpp2025-07-14 12:22 11K 
[TXT]SIInsertHardClauses.cpp2025-07-14 12:22 11K 
[ ]VINTERPInstructions.td2025-07-14 12:22 11K 
[TXT]R600EmitClauseMarkers.cpp2025-07-14 12:22 11K 
[TXT]AMDGPURewriteAGPRCopyMFMA.cpp2025-07-14 12:22 11K 
[TXT]AMDGPUPreLegalizerCombiner.cpp2025-07-14 12:22 10K 
[TXT]AMDGPURegBankSelect.cpp2025-07-14 12:22 10K 
[TXT]R600ExpandSpecialInstrs.cpp2025-07-14 12:22 9.8K 
[ ]R600RegisterInfo.td2023-07-06 06:03 9.8K 
[TXT]GCNPreRAOptimizations.cpp2025-07-14 12:22 9.7K 
[TXT]AMDGPULowerKernelArguments.cpp2025-07-14 12:22 9.6K 
[TXT]AMDGPURegBankLegalizeRules.h2025-07-14 12:22 9.5K 
[TXT]GCNVOPDUtils.cpp2025-07-14 12:22 9.5K 
[ ]AMDGPUCombine.td2025-07-14 12:22 8.9K 
[TXT]AMDGPUMachineFunction.cpp2025-07-14 12:22 8.7K 
[ ]GCNProcessors.td2025-07-14 12:22 8.3K 
[TXT]GCNMinRegStrategy.cpp2025-07-14 12:22 8.2K 
[ ]AMDGPUGenRegisterBankInfo.def2025-07-14 12:22 8.0K 
[ ]CaymanInstructions.td2023-07-06 06:03 7.9K 
[TXT]SIPreAllocateWWMRegs.cpp2025-07-14 12:22 7.8K 
[TXT]AMDGPUArgumentUsageInfo.cpp2025-07-14 12:22 7.8K 
[TXT]AMDGPUSetWavePriority.cpp2025-07-14 12:22 7.7K 
[TXT]AMDGPURegisterBankInfo.h2024-07-18 02:23 7.7K 
[ ]AMDGPUPassRegistry.def2025-07-14 12:22 7.7K 
[TXT]AMDGPUTargetMachine.h2025-07-14 12:22 7.6K 
[TXT]SIProgramInfo.cpp2025-07-14 12:22 7.6K 
[TXT]GCNCreateVOPD.cpp2025-07-14 12:22 7.5K 
[TXT]AMDGPURemoveIncompatibleFunctions.cpp2025-07-14 12:22 7.4K 
[TXT]AMDGPUPreloadKernArgProlog.cpp2025-07-14 12:22 7.4K 
[TXT]AMDGPUCtorDtorLowering.cpp2025-07-14 12:22 7.3K 
[TXT]SIPostRABundler.cpp2025-07-14 12:22 7.3K 
[TXT]R600ClauseMergePass.cpp2023-07-21 02:22 7.0K 
[TXT]AMDGPURewriteUndefForPHI.cpp2025-07-14 12:22 6.9K 
[TXT]R600ISelDAGToDAG.cpp2025-07-14 12:22 6.6K 
[TXT]R600TargetMachine.cpp2025-07-14 12:22 6.6K 
[ ]AMDGPUCallingConv.td2025-07-14 12:22 6.5K 
[TXT]AMDGPUPromoteKernelArguments.cpp2025-07-14 12:22 6.4K 
[ ]EXPInstructions.td2025-07-14 12:22 6.3K 
[TXT]CMakeLists.txt2025-07-14 12:22 6.1K 
[TXT]GCNPreRALongBranchReg.cpp2025-07-14 12:22 5.9K 
[TXT]AMDGPUGlobalISelUtils.cpp2025-07-14 12:22 5.8K 
[ ]DSDIRInstructions.td2025-07-14 12:22 5.8K 
[TXT]SIModeRegisterDefaults.h2025-07-14 12:22 5.7K 
[TXT]SILowerWWMCopies.cpp2025-07-14 12:22 5.7K 
[TXT]GCNHazardRecognizer.h2025-07-14 12:22 5.5K 
[TXT]R600TargetTransformInfo.cpp2025-07-14 12:22 5.5K 
[TXT]AMDGPUMachineModuleInfo.h2025-07-14 12:22 5.4K 
[TXT]R600ISelLowering.h2024-07-18 02:23 5.4K 
[TXT]AMDGPUHSAMetadataStreamer.h2025-07-14 12:22 5.4K 
[TXT]AMDGPUArgumentUsageInfo.h2025-07-14 12:22 5.3K 
[TXT]AMDGPUAlwaysInlinePass.cpp2025-07-14 12:22 5.3K 
[TXT]AMDGPUMarkLastScratchLoad.cpp2025-07-14 12:22 5.2K 
[TXT]AMDGPUAsmPrinter.h2025-07-14 12:22 5.0K 
[TXT]AMDGPUMIRFormatter.cpp2025-07-14 12:22 5.0K 
[TXT]SIFrameLowering.h2025-07-14 12:22 5.0K 
[TXT]AMDGPURegBankLegalizeHelper.h2025-07-14 12:22 4.9K 
[TXT]AMDGPUAnnotateUniformValues.cpp2025-07-14 12:22 4.7K 
[TXT]R600Subtarget.h2025-07-14 12:22 4.7K 
[TXT]R600AsmPrinter.cpp2023-07-21 02:22 4.4K 
[TXT]AMDGPUExportClustering.cpp2025-07-14 12:22 4.4K 
[TXT]AMDGPUAliasAnalysis.cpp2025-07-14 12:22 4.4K 
[ ]R600Processors.td2025-07-14 12:22 4.4K 
[TXT]R600Defines.h2023-07-06 06:03 4.2K 
[TXT]GCNIterativeScheduler.h2025-07-14 12:22 4.1K 
[TXT]AMDGPUUnifyMetadata.cpp2025-07-14 12:22 4.1K 
[TXT]AMDGPUMachineFunction.h2025-07-14 12:22 4.0K 
[TXT]SIProgramInfo.h2025-07-14 12:22 3.9K 
[TXT]AMDGPUMCResourceInfo.h2025-07-14 12:22 3.8K 
[TXT]R600RegisterInfo.cpp2023-07-21 02:22 3.8K 
[TXT]AMDGPUCallLowering.h2024-07-18 02:23 3.7K 
[TXT]SILowerI1Copies.h2025-07-14 12:22 3.5K 
[TXT]AMDGPUExportKernelRuntimeHandles.cpp2025-07-14 12:22 3.4K 
[TXT]AMDGPUReserveWWMRegs.cpp2025-07-14 12:22 3.4K 
[TXT]R600TargetTransformInfo.h2025-07-14 12:22 3.1K 
[TXT]AMDGPUAliasAnalysis.h2025-07-14 12:22 3.0K 
[TXT]R600TargetMachine.h2025-07-14 12:22 2.9K 
[TXT]AMDGPUResourceUsageAnalysis.h2025-07-14 12:22 2.8K 
[TXT]R600MCInstLower.cpp2025-07-14 12:22 2.7K 
[TXT]SIFixVGPRCopies.cpp2025-07-14 12:22 2.5K 
[TXT]R600MachineScheduler.h2025-07-14 12:22 2.5K 
[TXT]AMDGPUMemoryUtils.h2025-07-14 12:22 2.4K 
[TXT]AMDGPUMCInstLower.h2025-07-14 12:22 2.4K 
[TXT]AMDGPUMIRFormatter.h2025-07-14 12:22 2.3K 
[TXT]AMDGPUInstrInfo.h2025-07-14 12:22 2.3K 
[TXT]AMDGPUPerfHintAnalysis.h2025-07-14 12:22 2.3K 
[TXT]AMDGPUAsanInstrumentation.h2025-07-14 12:22 2.3K 
[TXT]AMDGPUMacroFusion.cpp2024-07-18 02:23 2.2K 
[ ]AMDGPUFeatures.td2025-07-14 12:22 2.0K 
[TXT]R600RegisterInfo.h2023-07-21 02:22 2.0K 
[TXT]AMDGPUFrameLowering.cpp2023-07-21 02:22 2.0K 
[TXT]R600Subtarget.cpp2025-07-14 12:22 1.9K 
[TXT]AMDGPUCombinerHelper.h2025-07-14 12:22 1.9K 
[TXT]AMDGPUGlobalISelUtils.h2025-07-14 12:22 1.8K 
[TXT]R600FrameLowering.cpp2023-07-21 02:22 1.7K 
[TXT]R600.h2025-07-14 12:22 1.7K 
[TXT]AMDGPUInstrInfo.cpp2025-07-14 12:22 1.7K 
[ ]AMDGPUAttributes.def2025-07-14 12:22 1.6K 
[ ]R600Schedule.td2023-07-06 06:03 1.6K 
[TXT]R600AsmPrinter.h2025-07-14 12:22 1.6K 
[ ]R600.td2025-07-14 12:22 1.5K 
[TXT]AMDGPUTargetObjectFile.cpp2024-07-18 02:23 1.5K 
[TXT]AMDGPUUnifyDivergentExitNodes.h2024-07-18 02:23 1.5K 
[TXT]AMDGPUFrameLowering.h2023-07-06 06:03 1.4K 
[TXT]AMDGPUMachineModuleInfo.cpp2025-07-14 12:22 1.3K 
[TXT]R600FrameLowering.h2025-07-14 12:22 1.3K 
[TXT]AMDGPUSplitModule.h2025-07-14 12:22 1.3K 
[ ]AMDGPUPredicateControl.td2025-07-14 12:22 1.2K 
[TXT]AMDGPUTargetObjectFile.h2023-07-06 06:03 1.1K 
[TXT]GCNVOPDUtils.h2025-07-14 12:22 1.1K 
[ ]AMDGPURegisterBanks.td2025-07-14 12:22 1.1K 
[TXT]SIOptimizeVGPRLiveRange.h2025-07-14 12:22 1.0K 
[TXT]SILowerSGPRSpills.h2025-07-14 12:22 1.0K 
[TXT]AMDGPURemoveIncompatibleFunctions.h2025-07-14 12:22 960  
[TXT]SILoadStoreOptimizer.h2025-07-14 12:22 942  
[TXT]SIFoldOperands.h2025-07-14 12:22 940  
[ ]R600InstrInfo.td2023-07-06 06:03 921  
[TXT]AMDGPUPTNote.h2023-07-06 06:03 913  
[TXT]SIWholeQuadMode.h2025-07-14 12:22 910  
[TXT]GCNDPPCombine.h2025-07-14 12:22 905  
[TXT]AMDGPUIGroupLP.h2025-07-14 12:22 892  
[TXT]AMDGPUReserveWWMRegs.h2025-07-14 12:22 868  
[TXT]R600MachineFunctionInfo.h2023-07-21 02:22 864  
[TXT]AMDGPUCtorDtorLowering.h2023-07-21 02:22 863  
[TXT]AMDGPUExportKernelRuntimeHandles.h2025-07-14 12:22 861  
[TXT]AMDGPUMacroFusion.h2025-07-14 12:22 860  
[TXT]SIOptimizeExecMaskingPreRA.h2025-07-14 12:22 854  
[TXT]AMDGPUPreloadKernArgProlog.h2025-07-14 12:22 845  
[TXT]GCNRewritePartialRegUses.h2025-07-14 12:22 844  
[TXT]SIShrinkInstructions.h2025-07-14 12:22 838  
[TXT]SIFixSGPRCopies.h2025-07-14 12:22 832  
[TXT]AMDGPUWaitSGPRHazards.h2025-07-14 12:22 831  
[TXT]SIOptimizeExecMasking.h2025-07-14 12:22 829  
[TXT]GCNPreRAOptimizations.h2025-07-14 12:22 829  
[TXT]GCNPreRALongBranchReg.h2025-07-14 12:22 829  
[TXT]SIPreAllocateWWMRegs.h2025-07-14 12:22 826  
[TXT]SIFormMemoryClauses.h2025-07-14 12:22 815  
[TXT]SILowerControlFlow.h2025-07-14 12:22 810  
[TXT]AMDGPUSelectionDAGInfo.h2025-07-14 12:22 805  
[TXT]SILowerWWMCopies.h2025-07-14 12:22 800  
[TXT]SIPostRABundler.h2025-07-14 12:22 795  
[TXT]SIFixVGPRCopies.h2025-07-14 12:22 795  
[TXT]SIPeepholeSDWA.h2025-07-14 12:22 792  
[TXT]GCNNSAReassign.h2025-07-14 12:22 790  
[ ]R700Instructions.td2023-07-06 06:03 783  
[TXT]AMDGPUExportClustering.h2023-07-06 06:03 726  
[TXT]AMDGPUSelectionDAGInfo.cpp2025-07-14 12:22 704  
[ ]VIInstrFormats.td2023-07-21 02:22 653  
[TXT]R600MachineFunctionInfo.cpp2023-07-21 02:22 651  
[ ]InstCombineTables.td2025-07-14 12:22 264  
[DIR]Utils/2025-07-14 12:22 -  
[DIR]TargetInfo/2025-07-14 12:22 -  
[DIR]MCTargetDesc/2025-07-14 12:22 -  
[DIR]MCA/2025-07-14 12:22 -  
[DIR]Disassembler/2025-07-14 12:22 -  
[DIR]AsmParser/2025-07-14 12:22 -  
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